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##---------------------------------------------------------------------
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# COPYRIGHT (C) 2020
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## This software and the associated documentation are confidential and
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## proprietary to 671.
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##
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## The entire notice above must be reproduced on all authorized copies.
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##----------------------------------------------------------------------
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SHELL := /bin/csh
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################## DC env ###########################################
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export DCWORK = ./dc.work
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export DC_FILELIST = ${DCWORK}/filelist.v
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export PP ?= ./
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export PROJECTPATH = $(shell $(SCRIPTPATH)/get_PROJECT_PATH.sh)
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export RELATIVEPATH = /home/UWE/zj/tmp
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#export RELATIVEPATH = /home/admin/liuchang/FrontEnd_Flow
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export SCRIPTPATH = $(RELATIVEPATH)/Scripts
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export TCLPATH = $(RELATIVEPATH)/Tcls
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export SDCPATH = $(PROJECTPATH)/syn/SDC
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export VPATH = $(SCRIPTPATH):$(TCLPATH):$(SDCPATH)
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export FLOW ?= FALSE
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export DEBUGSDC ?= FALSE
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export LOADDDC ?= FALSE
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export CHECKTIMING ?= FALSE
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export CHECKCODE ?= FALSE
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export FLAT ?= FALSE
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export PATH = $(VPATH):$(shell echo $$PATH)
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SOURCE_EDA_DC = source /space/CAD_Front_End/Synopsys/syn/syn_S-2021.06-SP4.setup
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SOURCE_EDA_PT = source /space/CAD_Front_End/Synopsys/prime/prime_S-2021.06-SP4.setup
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SOURCE_EDA_FM = source /space/CAD_Front_End/Synopsys/fm/fm_S-2021.06-SP4.setup
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SOURCE_EDA_LC = source /space/CAD_Front_End/Synopsys2020/lc/lc_R-2020.09-SP3.setup
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#SOURCE_EDA_DC = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
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#SOURCE_EDA_PT = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
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#SOURCE_EDA_FM = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
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#SOURCE_EDA_LC = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
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#export SNPSLMD_LICENSE_FILE = $(shell source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup && echo $$SNPSLMD_LICENSE_FILE)
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#export PATH = $(VPATH):$(shell source /space/CAD_Front_End/Synopsys2013/dc_2013.setup && source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup && echo $$PATH)
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###########################################################################
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################### Sim env ###############################################
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export NCWORK = ./nc.work
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export NC_FILELIST = ${NCWORK}/sim_filelist.f
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export DESIGN = $(shell $(SCRIPTPATH)/get_CURRENT_DESIGN.sh)
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export SIMULATOR ?= NC
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SOURCE_EDA_xcelium = source /space/CAD_Front_End/Cadence/xcelium/xcelium_2105001.setup
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SOURCE_EDA_indago = source /space/CAD_Front_End/Cadence/indago/indago_2105001.setup
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SOURCE_EDA_vmanager= source /space/CAD_Front_End/Cadence2020/vmanager_2003.setup
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SOURCE_EDA_verdi = source /space/CAD_Front_End/Synopsys/verdi/verdi_R-2020.12.setup
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SOURCE_EDA_vcs = source /space/CAD_Front_End/Synopsys/vcs/vcs_R-2020.12.setup
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XRUN = @${SOURCE_EDA_xcelium}; xrun -sv -access rwc -lwdgen -source_debug -work work -nospecify -run -64bit -nowarn CUNGL1 -nowarn NONPRT -timescale 1ns/1ps -parseinfo include
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SV = @${SOURCE_EDA_xcelium}; simvision -64bit
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INDAGO = @${SOURCE_EDA_indago} ; indago -wave_db
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XMVHDL = @${SOURCE_EDA_xcelium} ; xmvhdl -64bit -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright
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VCS = ${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vcs -full64 -sverilog -kdb -lca +nospecify -error=noMPD -debug_acc
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VCS_F = ${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vcs -full64 -sverilog -kdb -lca +nospecify -error=noMPD
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VERDI = ${SOURCE_EDA_verdi} ; ${SOURCE_EDA_vcs} ; verdi -nologo
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IMC = ${SOURCE_EDA_vmanager} ; imc -64bit -gui
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VHDLAN = @${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vhdlan -full64 -kdb
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VLOGAN = @${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vlogan -full64 -kdb -sverilog -error=noMPD
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CDSGEN = @${SOURCE_EDA_xcelium} ; $(SCRIPTPATH)/cds_gen
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###########################################################################
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################### Spyglass env ##########################################
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SOURCE_EDA_spyglass = source /space/CAD_Front_End/Synopsys/spyglass/spyglass_S-2021.09-SP1.setup
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export SPYGLASSWORK = ./spyglass.work
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#pre-define env variable. don't modify it
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export RUN_POWER_FLOW = no
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export RUN_CDC_FLOW = no
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export RUN_RDC_FLOW = no
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export RUN_CONSTRAINT_FLOW = no
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export RUN_TXV_FLOW = no
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#----------------------------------------
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export LINT_DONT_SET_TOP = no
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export USE_CUSTOM_METHODOLOGY = no
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export SG_CUSTOM_METHODOLOGY_DIR = $(SCRIPTPATH)/custom_methodology
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#export SG_SRC_FILELIST = src.f ????
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export SG_SRC_FILELIST = ${NC_FILELIST}
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export SG_TECH_LIBFILE = ${PROJECTPATH}/syn/spyglass_tech_lib.f
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export SG_REPORT_DIR = ${SPYGLASSWORK}/sg_results
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export top-module-name = ${DESIGN}
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###########################################################################
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################### EasyECO env ##########################################
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SOURCE_EDA_easyECO = source /home/admin/easyeco-release-2022_04_13_17_01_32/easyECO.setup
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export ECO_COMM ?= ECO
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###########################################################################
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current_date = $(shell date +%Y_%m%d_%H%M)
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lec:
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@${SOURCE_EDA_easyECO}; ./ezlec.sh
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eco:
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@${SOURCE_EDA_easyECO}; ./ezeco.sh
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autoeco:
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@${SOURCE_EDA_easyECO}; ${SOURCE_EDA_FM}; ./auto_eco.sh
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help:
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@echo "###########################################################################"
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@echo " -------"
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@echo " | |"
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@echo " | * * |"
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@echo " | ? |"
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@echo " | |"
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@echo " | (_) |"
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@echo " ---------"
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@echo ""
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@echo "If encountering problems during use, please checking the following:"
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@echo "Checking ProjectPathSetting.tcl."
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@echo "Checking filelist.v."
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@echo "Checking setModuleName.tcl."
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@echo "Checking RELATIVEPATH in Makefile."
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@echo "Checking syn_specific.tcl."
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@echo "Checking synopsys_dc.setup."
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@echo "Checking whether all linked library are in the *db* folder."
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@echo ""
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@echo "SYNTAX"
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@echo " make"
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@echo " [Prepare] : Create a working environment."
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@echo " [clean] : Clean all temporary files."
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@echo " [help] : make help."
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@echo " [xrun] : Start the NC tool for simulation."
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@echo " [xrun_nogui] : Start the NC tool for simulation without gui."
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@echo " [indago] : Start the indago tool for debugging."
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@echo " [sim] : Same as make xrun."
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@echo " [design_audit] : Check spyglass running environment."
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@echo " [lint] : Start the spyglass tool for checking lint."
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@echo " [cdc] : Start the spyglass tool for checking cdc."
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@echo " [code_check_all] : Check whether the code meets the submission requirements."
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@echo " [c_k] : make check_warning, find all warnings"
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@echo " [c_e] : make check_error, find all errors in dc.log"
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@echo " [c_R0] [PP=*] : R0 check in dc.log, pt.log, fm.log, need to give check path, default ./ ."
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@echo " [pt] [PP=*] : make pt, generate check_timing_pt.txt and .lib, need to give check path, default ./ ."
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@echo " [l2d] [PP=*] : make lib2db, need to give check path, default ./ ."
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@echo " [check][PP=*] : make c_R0, pt and fomality, need to give check path, default ./ ."
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@echo " [svn] [PP=*] : copy submit files into Netlist, and svn commit. need to give check path, default ./ ."
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@echo " [submit] [PP=*] : l2d, copy_sdc, svn. need to give check path, default ./ ."
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@echo " [f] [PP=*] : make fomality, need to give check path, default ./ ."
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@echo " [syn] : make synthesize, use syn_main.tcl, "
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@echo " [flow] : make syn, check, and submit."
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@echo " [gen_fl] : generate the filelist of current module."
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@echo " [tab_c] : check the tab in RTL code, and change it into n space."
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@echo "#################################################"
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######################################################################
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# Sim
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######################################################################
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begin: simclean
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@echo "=============compiling ft-m7004 rtl codes=============="
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@echo "NOTE: current code source path is: " ${PROJECTPATH}" "
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ln -snf ${PROJECTPATH}/src/BOOT/rtl/RBL_512w128b_ROM1.hex RBL_512w128b_ROM1.hex
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ln -snf ${PROJECTPATH}/src/BOOT/rtl/RBL_512w128b_ROM2.hex RBL_512w128b_ROM2.hex
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compile_vhd: cds
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./nc.work/sim_specific.sh ${SIMULATOR}
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xrun: begin compile_vhd
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@${XRUN} -gui -top ${DESIGN} -define _SIMULATION_ -f ${NC_FILELIST}
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xrun_nogui: begin compile_vhd
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@${XRUN} -top ${DESIGN} -define _SIMULATION_ -exit -f ${NC_FILELIST}
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vcs: export SIMULATOR = VCS
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vcs: begin compile_vhd
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@${VLOGAN} -f ${NC_FILELIST} +define+_SIMULATION_ | tee vcs.log
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@${VCS} -top ${DESIGN} -R | tee -a vcs.log
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vcsfast:begin_vcs
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@${VLOGAN} -f ${NC_FILELIST} | tee vcs.log
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@${VCS_F} -top ${DESIGN} -R | tee -a vcs.log
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sv:
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@${SV}
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indago:
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@${INDAGO} ${DESIGN}.shm
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sim: xrun_nogui
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#verdinet: export NOVAS_LIBS="/home/admin/liuchang/M7004V/syn/db/RHSTD_LVT_ssg0p72vm40c_ccs.lib /home/admin/liuchang/M7004V/syn/db/RHSTD_RVT_ssg0p72vm40c_ccs.lib"
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#@${VERDI} -novasLibs "RHSTD_LVT_ssg0p72vm40c_ccs.lib++ RHSTD_RVT_ssg0p72vm40c_ccs.lib++" -dbdir simv.daidir
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verdinet:
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@${VLOGAN} -f ${NC_FILELIST} $(PP)/result/${DESIGN}.sv +define+_SIMULATION_ | tee vcs.log
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@${VCS_F} -top ${DESIGN} | tee -a vcs.log
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@${VERDI} -dbdir simv.daidir
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verdi:
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@${VERDI} -ssf ${DESIGN}.fsdb
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cds:
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@${CDSGEN}
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######################################################################
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# Spyglass
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######################################################################
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#setup:
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# ln -snf /space/CAD_Front_End/Synopsys/spyglass/pdf/lint/spyglass_lint_reference_manul_gfkdwdzs_V1.pdf spyglass_lint_reference.pdf
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# mv ethmac.prj ${top-module-name}.prj
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# mv waiver/ethmac.awl waiver/${top-module-name}.awl
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link_spyglass_reference:
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ln -snf /space/CAD_Front_End/Synopsys/spyglass/pdf/lint/spyglass_lint_reference_manul_gfkdwdzs_V1.pdf spyglass_lint_Error_Warning_reference.pdf
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design_audit:
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal lint/design_audit
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gvim ${SG_REPORT_DIR}/${top-module-name}/consolidated_reports/${top-module-name}_lint_design_audit/Audit.rpt
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lint: link_spyglass_reference
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal lint/lint_rtl
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#gvim ${SG_REPORT_DIR}/${top-module-name}/consolidated_reports/${top-module-name}_lint_lint_rtl/moresimple.rpt
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cdc: cdc_setup_check clock_reset_integrity cdc_verify_struct
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cdc_setup:
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export RUN_CDC_FLOW=yes;\
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_setup
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@echo "=========INFO: SpyGlass would automatically extract design clock/reset constraint ==========="
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@echo "=========INFO: User can refer to below files and modify the clock domain as required ==========="
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@echo "=========INFO: Then user can add the refined cosntraints in the top design sgdc file ==========="
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@echo "egrep \"^clock\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/autoclocks.sgdc"
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@echo "egrep \"^clock\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/generated_clocks.sgdc"
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@echo "egrep \"^reset\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/autoresets.sgdc"
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@echo "egrep \"^reset\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/generated_resets.sgdc"
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@echo "egrep \"^set_case_analysis\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/auto_case_analysis.sgdc"
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cdc_setup_check:
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export RUN_CDC_FLOW=yes;\
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_setup_check
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@echo "=========INFO: If there were any unconstraint primary ports and bbox ==========="
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@echo "=========INFO: SpyGlass would automatically generate a template cdc constriant for them ==========="
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@echo "=========INFO: User can refer to below two files and modify related port clock as required ==========="
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@echo "=========INFO: Then user can add the refined cosntraints in the top design sgdc file ==========="
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@echo "egrep \"^abstract_port\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup_check/spyglass_reports/clock-reset/${top-module-name}_input_abstract.sgdc"
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@echo "egrep \"^abstract_port\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup_check/spyglass_reports/clock-reset/Setup_blackbox01/${top-module-name}_bbox_model.sgdc"
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clock_reset_integrity:
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export RUN_CDC_FLOW=yes;\
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/clock_reset_integrity
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cdc_verify_struct:
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export RUN_CDC_FLOW=yes;\
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_verify_struct
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cdc_verify:
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export RUN_CDC_FLOW=yes;\
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_verify
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rdc:
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export RUN_RDC_FLOW=yes;\
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal rdc/rdc_verify_struct
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power_audit:
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export RUN_POWER_FLOW=yes;\
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_audit
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power_activity_check:
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export RUN_POWER_FLOW=yes;\
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@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_activity_check
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||||
power_est_profiling:
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export RUN_POWER_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_est_profiling
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||||
power_cge_profiling:
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export RUN_POWER_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_cge_profiling
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||||
power: export RUN_POWER_FLOW = yes
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||||
power:
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_audit,power/power_activity_check,power/power_est_profiling
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exec mkdir ./spyglass.work/${top-module-name}_${current_date}
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||||
exec cp -r ./spyglass.work/sg_results/${top-module-name}/consolidated_reports/* ./spyglass.work/${top-module-name}_${current_date}/
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||||
sdc_gen:
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||||
export RUN_CONSTRAINT_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_gen
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||||
sdc_audit:
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||||
export RUN_CONSTRAINT_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_audit
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||||
sdc_check:
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||||
export RUN_CONSTRAINT_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_check
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||||
sdc_exception_struct:
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||||
export RUN_CONSTRAINT_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_exception_struct
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||||
sdc_redundancy:
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||||
export RUN_CONSTRAINT_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_redundancy
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||||
sdc_equiv:
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||||
export RUN_CONSTRAINT_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_equiv
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||||
sdc_hier_equiv:
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||||
export RUN_CONSTRAINT_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_hier_equiv
|
||||
sdc:
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||||
export RUN_CONSTRAINT_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_audit,constraints/sdc_check,constraints/sdc_exception_struct,constraints/sdc_redundancy
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||||
fp_verification:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/fp_verification
|
||||
mcp_verification:
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||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/mcp_verification
|
||||
txv:
|
||||
export RUN_TXV_FLOW=yes;\
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||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/fp_mcp_verification
|
||||
|
||||
lintgui:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
cdcgui:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
|
||||
rdcgui:
|
||||
export RUN_RDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
sdcgui:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
txvgui:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
powergui: export RUN_POWER_FLOW = yes
|
||||
powergui:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
|
||||
######################################################################
|
||||
# Genus
|
||||
######################################################################
|
||||
genus : genusclean
|
||||
@/space/CAD_Back_End/Cadence20/GENUS201/bin/genus -file $(TCLPATH)/genus_flow.tcl
|
||||
|
||||
######################################################################
|
||||
# DC, PT & FM
|
||||
######################################################################
|
||||
syn : synclean Prepare
|
||||
@${SOURCE_EDA_DC}; dc_shell-t -f $(TCLPATH)/syn_main.tcl | tee dc.log ${DCWORK}/Logs/dc_${current_date}.log
|
||||
|
||||
get_DBs_info:
|
||||
$(SCRIPTPATH)/get_DBs_info.sh
|
||||
|
||||
report_dc_summary:
|
||||
$(SCRIPTPATH)/report_dc_summary.sh
|
||||
|
||||
c_w:
|
||||
$(SCRIPTPATH)/warning_find.perl
|
||||
|
||||
c_e:
|
||||
$(SCRIPTPATH)/error_find.perl
|
||||
|
||||
code_check_all: CHECKCODE = TRUE
|
||||
code_check_all: c_SRC_ID sim syn lint
|
||||
$(SCRIPTPATH)/check_code.sh
|
||||
gvim code_check.result
|
||||
|
||||
code_check:
|
||||
$(SCRIPTPATH)/check_code.sh
|
||||
gvim code_check.result
|
||||
|
||||
c_SRC_ID:
|
||||
$(SCRIPTPATH)/check_SRC_ID.sh
|
||||
|
||||
c_R0:
|
||||
$(SCRIPTPATH)/check_R0.sh
|
||||
|
||||
gen_fl:
|
||||
$(SCRIPTPATH)/filelist_gen.sh
|
||||
|
||||
tab_c:
|
||||
$(SCRIPTPATH)/tab_change
|
||||
|
||||
pt: Prepare
|
||||
@${SOURCE_EDA_PT}; pt_shell -f $(TCLPATH)/pt.tcl | tee pt.log pt_${current_date}.log
|
||||
mv pt_${current_date}.log ${DCWORK}/Logs
|
||||
|
||||
l2d:
|
||||
@echo $(PP)
|
||||
@${SOURCE_EDA_LC}; lc_shell -f $(TCLPATH)/lib_to_db.tcl | tee lib2db.log
|
||||
|
||||
check: pt f c_R0
|
||||
|
||||
submit: l2d copy_sdc svn
|
||||
|
||||
run_all:
|
||||
$(SCRIPTPATH)/runAll.sh
|
||||
|
||||
svn: copy_sdc
|
||||
$(SCRIPTPATH)/SVNSubmit.sh
|
||||
|
||||
setPP:
|
||||
@echo $(PP)
|
||||
$(SCRIPTPATH)/setPP.sh
|
||||
@echo $(PP)
|
||||
|
||||
copy_sdc:
|
||||
@echo $(PP)
|
||||
$(SCRIPTPATH)/copy_sdc.sh
|
||||
|
||||
f:
|
||||
@${SOURCE_EDA_FM}; fm_shell -64 -f $(TCLPATH)/formality.tcl | tee fm.log ${DCWORK}/Logs/fm_${current_date}.log
|
||||
|
||||
flow : export FLOW = TRUE
|
||||
flow: syn pt submit f c_R0
|
||||
|
||||
cplib2db:
|
||||
@${SOURCE_EDA_DC}; dc_shell -f $(TCLPATH)/copyLib.tcl
|
||||
cd ../db-8024/ && lib2db.tcl
|
||||
|
||||
Prepare:
|
||||
$(SCRIPTPATH)/quick_start
|
||||
|
||||
############################
|
||||
## CLEAN
|
||||
############################
|
||||
.PHONY: simclean
|
||||
simclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf xcelium.d xrun.log xrun.key xrun.history novas_dump.log Log waves_M7004v.shm indago_logs_backup cdns_dump.log indago_logs xncsim xmvhdl.log hdl.var
|
||||
@rm -rf cds.lib error.log warn.log log .indago_auto_save .simvision synopsys_sim.setup simv waves_M7004v.fsdb .bpad Printout all_stimulation/ddr0_ini_path0.dat RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex
|
||||
|
||||
.PHONY: vcsclean
|
||||
vcsclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf simv.daidir csrc vcs_lib verdiLog novas.rc verdi_config_file novas.conf ucli.key vc_hdrs.h vcs.log RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex
|
||||
|
||||
.PHONY: synclean
|
||||
synclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf xxxxa.log dc.log pt.log formality.log fm_shell_command.log RTL_DC_info.log command.log analyzed alib-52 default.svf synopsysdc
|
||||
|
||||
.PHONY: sgclean
|
||||
sgclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf ./sypglass.work/sg_results *.out xxxxa.log
|
||||
|
||||
.PHONY: genusclean
|
||||
genusclean:
|
||||
@touch genus.log
|
||||
@rm -rf genus.*
|
||||
|
||||
.PHONY: cleanall
|
||||
cleanall:
|
||||
@rm -rf analyzed alib-52 default.svf synopsysdc xcelium.d xrun.key xrun.history Log *.shm indago_logs ./sypglass.work/sg_results *.log *.out *.shm xncsim hdl.var simv.daidir csrc vcs_lib verdiLog novas.rc verdi_config_file novas.conf ucli.key vc_hdrs.h RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex cds.lib .indago_auto_save .simvision synopsys_sim.setup simv *.fsdb .bpad Printout
|
||||
|
||||
|
||||
@ -1,440 +0,0 @@
|
||||
##---------------------------------------------------------------------
|
||||
# COPYRIGHT (C) 2020
|
||||
## This software and the associated documentation are confidential and
|
||||
## proprietary to 671.
|
||||
##
|
||||
## The entire notice above must be reproduced on all authorized copies.
|
||||
##----------------------------------------------------------------------
|
||||
SHELL := /bin/csh
|
||||
|
||||
################## DC env ###########################################
|
||||
export DCWORK = ./dc.work
|
||||
export DC_FILELIST = ${DCWORK}/filelist.v
|
||||
export PP ?= ./
|
||||
export PROJECTPATH = $(shell $(SCRIPTPATH)/get_PROJECT_PATH.sh)
|
||||
export RELATIVEPATH = /home/UWE/zj/tmp
|
||||
#export RELATIVEPATH = /home/admin/liuchang/FrontEnd_Flow
|
||||
export SCRIPTPATH = $(RELATIVEPATH)/Scripts
|
||||
export TCLPATH = $(RELATIVEPATH)/Tcls
|
||||
export SDCPATH = $(PROJECTPATH)/syn/SDC
|
||||
export VPATH = $(SCRIPTPATH):$(TCLPATH):$(SDCPATH)
|
||||
export FLOW ?= FALSE
|
||||
export DEBUGSDC ?= FALSE
|
||||
export LOADDDC ?= FALSE
|
||||
export CHECKTIMING ?= FALSE
|
||||
export CHECKCODE ?= FALSE
|
||||
export FLAT ?= FALSE
|
||||
export PATH = $(VPATH):$(shell echo $$PATH)
|
||||
SOURCE_EDA_DC = source /space/CAD_Front_End/Synopsys/syn/syn_S-2021.06-SP4.setup
|
||||
SOURCE_EDA_PT = source /space/CAD_Front_End/Synopsys/prime/prime_S-2021.06-SP4.setup
|
||||
SOURCE_EDA_FM = source /space/CAD_Front_End/Synopsys/fm/fm_S-2021.06-SP4.setup
|
||||
SOURCE_EDA_LC = source /space/CAD_Front_End/Synopsys2020/lc/lc_R-2020.09-SP3.setup
|
||||
#SOURCE_EDA_DC = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
|
||||
#SOURCE_EDA_PT = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
|
||||
#SOURCE_EDA_FM = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
|
||||
#SOURCE_EDA_LC = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
|
||||
#export SNPSLMD_LICENSE_FILE = $(shell source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup && echo $$SNPSLMD_LICENSE_FILE)
|
||||
#export PATH = $(VPATH):$(shell source /space/CAD_Front_End/Synopsys2013/dc_2013.setup && source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup && echo $$PATH)
|
||||
###########################################################################
|
||||
|
||||
################### Sim env ###############################################
|
||||
export NCWORK = ./nc.work
|
||||
export NC_FILELIST = ${NCWORK}/sim_filelist.f
|
||||
export DESIGN = $(shell $(SCRIPTPATH)/get_CURRENT_DESIGN.sh)
|
||||
export SIMULATOR ?= NC
|
||||
|
||||
SOURCE_EDA_xcelium = source /space/CAD_Front_End/Cadence/xcelium/xcelium_2105001.setup
|
||||
SOURCE_EDA_indago = source /space/CAD_Front_End/Cadence/indago/indago_2105001.setup
|
||||
SOURCE_EDA_vmanager= source /space/CAD_Front_End/Cadence2020/vmanager_2003.setup
|
||||
SOURCE_EDA_verdi = source /space/CAD_Front_End/Synopsys/verdi/verdi_R-2020.12.setup
|
||||
SOURCE_EDA_vcs = source /space/CAD_Front_End/Synopsys/vcs/vcs_R-2020.12.setup
|
||||
XRUN = @${SOURCE_EDA_xcelium}; xrun -sv -access rwc -lwdgen -source_debug -work work -nospecify -run -64bit -nowarn CUNGL1 -nowarn NONPRT -timescale 1ns/1ps -parseinfo include
|
||||
SV = @${SOURCE_EDA_xcelium}; simvision -64bit
|
||||
INDAGO = @${SOURCE_EDA_indago} ; indago -wave_db
|
||||
XMVHDL = @${SOURCE_EDA_xcelium} ; xmvhdl -64bit -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright
|
||||
VCS = ${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vcs -full64 -sverilog -kdb -lca +nospecify -error=noMPD -debug_acc
|
||||
VCS_F = ${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vcs -full64 -sverilog -kdb -lca +nospecify -error=noMPD
|
||||
VERDI = ${SOURCE_EDA_verdi} ; ${SOURCE_EDA_vcs} ; verdi -nologo
|
||||
IMC = ${SOURCE_EDA_vmanager} ; imc -64bit -gui
|
||||
VHDLAN = @${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vhdlan -full64 -kdb
|
||||
VLOGAN = @${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vlogan -full64 -kdb -sverilog -error=noMPD
|
||||
CDSGEN = @${SOURCE_EDA_xcelium} ; $(SCRIPTPATH)/cds_gen
|
||||
###########################################################################
|
||||
|
||||
################### Spyglass env ##########################################
|
||||
SOURCE_EDA_spyglass = source /space/CAD_Front_End/Synopsys/spyglass/spyglass_S-2021.09-SP1.setup
|
||||
export SPYGLASSWORK = ./spyglass.work
|
||||
#pre-define env variable. don't modify it
|
||||
export RUN_POWER_FLOW = no
|
||||
export RUN_CDC_FLOW = no
|
||||
export RUN_RDC_FLOW = no
|
||||
export RUN_CONSTRAINT_FLOW = no
|
||||
export RUN_TXV_FLOW = no
|
||||
#----------------------------------------
|
||||
export LINT_DONT_SET_TOP = no
|
||||
export USE_CUSTOM_METHODOLOGY = no
|
||||
export SG_CUSTOM_METHODOLOGY_DIR = $(SCRIPTPATH)/custom_methodology
|
||||
#export SG_SRC_FILELIST = src.f ????
|
||||
export SG_SRC_FILELIST = ${NC_FILELIST}
|
||||
export SG_TECH_LIBFILE = ${PROJECTPATH}/syn/spyglass_tech_lib.f
|
||||
export SG_REPORT_DIR = ${SPYGLASSWORK}/sg_results
|
||||
export top-module-name = ${DESIGN}
|
||||
###########################################################################
|
||||
|
||||
################### EasyECO env ##########################################
|
||||
SOURCE_EDA_easyECO = source /home/admin/easyeco-release-2022_04_13_17_01_32/easyECO.setup
|
||||
export ECO_COMM ?= ECO
|
||||
|
||||
###########################################################################
|
||||
|
||||
current_date = $(shell date +%Y_%m%d_%H%M)
|
||||
|
||||
lec:
|
||||
@${SOURCE_EDA_easyECO}; ./ezlec.sh
|
||||
|
||||
eco:
|
||||
@${SOURCE_EDA_easyECO}; ./ezeco.sh
|
||||
|
||||
autoeco:
|
||||
@${SOURCE_EDA_easyECO}; ${SOURCE_EDA_FM}; ./auto_eco.sh
|
||||
|
||||
help:
|
||||
@echo "###########################################################################"
|
||||
@echo " -------"
|
||||
@echo " | |"
|
||||
@echo " | * * |"
|
||||
@echo " | ? |"
|
||||
@echo " | |"
|
||||
@echo " | (_) |"
|
||||
@echo " ---------"
|
||||
@echo ""
|
||||
@echo "If encountering problems during use, please checking the following:"
|
||||
@echo "Checking ProjectPathSetting.tcl."
|
||||
@echo "Checking filelist.v."
|
||||
@echo "Checking setModuleName.tcl."
|
||||
@echo "Checking RELATIVEPATH in Makefile."
|
||||
@echo "Checking syn_specific.tcl."
|
||||
@echo "Checking synopsys_dc.setup."
|
||||
@echo "Checking whether all linked library are in the *db* folder."
|
||||
@echo ""
|
||||
@echo "SYNTAX"
|
||||
@echo " make"
|
||||
@echo " [Prepare] : Create a working environment."
|
||||
@echo " [clean] : Clean all temporary files."
|
||||
@echo " [help] : make help."
|
||||
@echo " [xrun] : Start the NC tool for simulation."
|
||||
@echo " [xrun_nogui] : Start the NC tool for simulation without gui."
|
||||
@echo " [indago] : Start the indago tool for debugging."
|
||||
@echo " [sim] : Same as make xrun."
|
||||
@echo " [design_audit] : Check spyglass running environment."
|
||||
@echo " [lint] : Start the spyglass tool for checking lint."
|
||||
@echo " [cdc] : Start the spyglass tool for checking cdc."
|
||||
@echo " [code_check_all] : Check whether the code meets the submission requirements."
|
||||
@echo " [c_k] : make check_warning, find all warnings"
|
||||
@echo " [c_e] : make check_error, find all errors in dc.log"
|
||||
@echo " [c_R0] [PP=*] : R0 check in dc.log, pt.log, fm.log, need to give check path, default ./ ."
|
||||
@echo " [pt] [PP=*] : make pt, generate check_timing_pt.txt and .lib, need to give check path, default ./ ."
|
||||
@echo " [l2d] [PP=*] : make lib2db, need to give check path, default ./ ."
|
||||
@echo " [check][PP=*] : make c_R0, pt and fomality, need to give check path, default ./ ."
|
||||
@echo " [svn] [PP=*] : copy submit files into Netlist, and svn commit. need to give check path, default ./ ."
|
||||
@echo " [submit] [PP=*] : l2d, copy_sdc, svn. need to give check path, default ./ ."
|
||||
@echo " [f] [PP=*] : make fomality, need to give check path, default ./ ."
|
||||
@echo " [syn] : make synthesize, use syn_main.tcl, "
|
||||
@echo " [flow] : make syn, check, and submit."
|
||||
@echo " [gen_fl] : generate the filelist of current module."
|
||||
@echo " [tab_c] : check the tab in RTL code, and change it into n space."
|
||||
@echo "#################################################"
|
||||
|
||||
######################################################################
|
||||
# Sim
|
||||
######################################################################
|
||||
begin: simclean
|
||||
@echo "=============compiling ft-m7004 rtl codes=============="
|
||||
@echo "NOTE: current code source path is: " ${PROJECTPATH}" "
|
||||
ln -snf ${PROJECTPATH}/src/BOOT/rtl/RBL_512w128b_ROM1.hex RBL_512w128b_ROM1.hex
|
||||
ln -snf ${PROJECTPATH}/src/BOOT/rtl/RBL_512w128b_ROM2.hex RBL_512w128b_ROM2.hex
|
||||
|
||||
compile_vhd: cds
|
||||
./nc.work/sim_specific.sh ${SIMULATOR}
|
||||
|
||||
xrun: begin compile_vhd
|
||||
@${XRUN} -gui -top ${DESIGN} -define _SIMULATION_ -f ${NC_FILELIST}
|
||||
|
||||
xrun_nogui: begin compile_vhd
|
||||
@${XRUN} -top ${DESIGN} -define _SIMULATION_ -exit -f ${NC_FILELIST}
|
||||
|
||||
vcs: export SIMULATOR = VCS
|
||||
vcs: begin compile_vhd
|
||||
@${VLOGAN} -f ${NC_FILELIST} +define+_SIMULATION_ | tee vcs.log
|
||||
@${VCS} -top ${DESIGN} -R | tee -a vcs.log
|
||||
|
||||
vcsfast:begin_vcs
|
||||
@${VLOGAN} -f ${NC_FILELIST} | tee vcs.log
|
||||
@${VCS_F} -top ${DESIGN} -R | tee -a vcs.log
|
||||
|
||||
sv:
|
||||
@${SV}
|
||||
|
||||
indago:
|
||||
@${INDAGO} ${DESIGN}.shm
|
||||
|
||||
sim: xrun_nogui
|
||||
|
||||
|
||||
#verdinet: export NOVAS_LIBS="/home/admin/liuchang/M7004V/syn/db/RHSTD_LVT_ssg0p72vm40c_ccs.lib /home/admin/liuchang/M7004V/syn/db/RHSTD_RVT_ssg0p72vm40c_ccs.lib"
|
||||
#@${VERDI} -novasLibs "RHSTD_LVT_ssg0p72vm40c_ccs.lib++ RHSTD_RVT_ssg0p72vm40c_ccs.lib++" -dbdir simv.daidir
|
||||
|
||||
verdinet:
|
||||
@${VLOGAN} -f ${NC_FILELIST} $(PP)/result/${DESIGN}.sv +define+_SIMULATION_ | tee vcs.log
|
||||
@${VCS_F} -top ${DESIGN} | tee -a vcs.log
|
||||
@${VERDI} -dbdir simv.daidir
|
||||
|
||||
verdi:
|
||||
@${VERDI} -ssf ${DESIGN}.fsdb
|
||||
|
||||
cds:
|
||||
@${CDSGEN}
|
||||
|
||||
######################################################################
|
||||
# Spyglass
|
||||
######################################################################
|
||||
#setup:
|
||||
# ln -snf /space/CAD_Front_End/Synopsys/spyglass/pdf/lint/spyglass_lint_reference_manul_gfkdwdzs_V1.pdf spyglass_lint_reference.pdf
|
||||
# mv ethmac.prj ${top-module-name}.prj
|
||||
# mv waiver/ethmac.awl waiver/${top-module-name}.awl
|
||||
|
||||
link_spyglass_reference:
|
||||
ln -snf /space/CAD_Front_End/Synopsys/spyglass/pdf/lint/spyglass_lint_reference_manul_gfkdwdzs_V1.pdf spyglass_lint_Error_Warning_reference.pdf
|
||||
|
||||
design_audit:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal lint/design_audit
|
||||
gvim ${SG_REPORT_DIR}/${top-module-name}/consolidated_reports/${top-module-name}_lint_design_audit/Audit.rpt
|
||||
|
||||
lint: link_spyglass_reference
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal lint/lint_rtl
|
||||
|
||||
#gvim ${SG_REPORT_DIR}/${top-module-name}/consolidated_reports/${top-module-name}_lint_lint_rtl/moresimple.rpt
|
||||
|
||||
cdc: cdc_setup_check clock_reset_integrity cdc_verify_struct
|
||||
|
||||
cdc_setup:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_setup
|
||||
@echo "=========INFO: SpyGlass would automatically extract design clock/reset constraint ==========="
|
||||
@echo "=========INFO: User can refer to below files and modify the clock domain as required ==========="
|
||||
@echo "=========INFO: Then user can add the refined cosntraints in the top design sgdc file ==========="
|
||||
@echo "egrep \"^clock\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/autoclocks.sgdc"
|
||||
@echo "egrep \"^clock\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/generated_clocks.sgdc"
|
||||
@echo "egrep \"^reset\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/autoresets.sgdc"
|
||||
@echo "egrep \"^reset\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/generated_resets.sgdc"
|
||||
@echo "egrep \"^set_case_analysis\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/auto_case_analysis.sgdc"
|
||||
cdc_setup_check:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_setup_check
|
||||
@echo "=========INFO: If there were any unconstraint primary ports and bbox ==========="
|
||||
@echo "=========INFO: SpyGlass would automatically generate a template cdc constriant for them ==========="
|
||||
@echo "=========INFO: User can refer to below two files and modify related port clock as required ==========="
|
||||
@echo "=========INFO: Then user can add the refined cosntraints in the top design sgdc file ==========="
|
||||
@echo "egrep \"^abstract_port\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup_check/spyglass_reports/clock-reset/${top-module-name}_input_abstract.sgdc"
|
||||
@echo "egrep \"^abstract_port\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup_check/spyglass_reports/clock-reset/Setup_blackbox01/${top-module-name}_bbox_model.sgdc"
|
||||
clock_reset_integrity:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/clock_reset_integrity
|
||||
cdc_verify_struct:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_verify_struct
|
||||
cdc_verify:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_verify
|
||||
rdc:
|
||||
export RUN_RDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal rdc/rdc_verify_struct
|
||||
power_audit:
|
||||
export RUN_POWER_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_audit
|
||||
power_activity_check:
|
||||
export RUN_POWER_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_activity_check
|
||||
power_est_profiling:
|
||||
export RUN_POWER_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_est_profiling
|
||||
power_cge_profiling:
|
||||
export RUN_POWER_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_cge_profiling
|
||||
power: export RUN_POWER_FLOW = yes
|
||||
power:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_audit,power/power_activity_check,power/power_est_profiling
|
||||
exec mkdir ./spyglass.work/${top-module-name}_${current_date}
|
||||
exec cp -r ./spyglass.work/sg_results/${top-module-name}/consolidated_reports/* ./spyglass.work/${top-module-name}_${current_date}/
|
||||
sdc_gen:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_gen
|
||||
sdc_audit:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_audit
|
||||
sdc_check:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_check
|
||||
sdc_exception_struct:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_exception_struct
|
||||
sdc_redundancy:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_redundancy
|
||||
sdc_equiv:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_equiv
|
||||
sdc_hier_equiv:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_hier_equiv
|
||||
sdc:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_audit,constraints/sdc_check,constraints/sdc_exception_struct,constraints/sdc_redundancy
|
||||
fp_verification:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/fp_verification
|
||||
mcp_verification:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/mcp_verification
|
||||
txv:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/fp_mcp_verification
|
||||
|
||||
lintgui:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
cdcgui:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
|
||||
rdcgui:
|
||||
export RUN_RDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
sdcgui:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
txvgui:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
powergui: export RUN_POWER_FLOW = yes
|
||||
powergui:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
|
||||
######################################################################
|
||||
# Genus
|
||||
######################################################################
|
||||
genus : genusclean
|
||||
@/space/CAD_Back_End/Cadence20/GENUS201/bin/genus -file $(TCLPATH)/genus_flow.tcl
|
||||
|
||||
######################################################################
|
||||
# DC, PT & FM
|
||||
######################################################################
|
||||
syn : synclean Prepare
|
||||
@${SOURCE_EDA_DC}; dc_shell-t -f $(TCLPATH)/syn_main.tcl | tee dc.log ${DCWORK}/Logs/dc_${current_date}.log
|
||||
|
||||
get_DBs_info:
|
||||
$(SCRIPTPATH)/get_DBs_info.sh
|
||||
|
||||
report_dc_summary:
|
||||
$(SCRIPTPATH)/report_dc_summary.sh
|
||||
|
||||
c_w:
|
||||
$(SCRIPTPATH)/warning_find.perl
|
||||
|
||||
c_e:
|
||||
$(SCRIPTPATH)/error_find.perl
|
||||
|
||||
code_check_all: CHECKCODE = TRUE
|
||||
code_check_all: c_SRC_ID sim syn lint
|
||||
$(SCRIPTPATH)/check_code.sh
|
||||
gvim code_check.result
|
||||
|
||||
code_check:
|
||||
$(SCRIPTPATH)/check_code.sh
|
||||
gvim code_check.result
|
||||
|
||||
c_SRC_ID:
|
||||
$(SCRIPTPATH)/check_SRC_ID.sh
|
||||
|
||||
c_R0:
|
||||
$(SCRIPTPATH)/check_R0.sh
|
||||
|
||||
gen_fl:
|
||||
$(SCRIPTPATH)/filelist_gen.sh
|
||||
|
||||
tab_c:
|
||||
$(SCRIPTPATH)/tab_change
|
||||
|
||||
pt: Prepare
|
||||
@${SOURCE_EDA_PT}; pt_shell -f $(TCLPATH)/pt.tcl | tee pt.log pt_${current_date}.log
|
||||
mv pt_${current_date}.log ${DCWORK}/Logs
|
||||
|
||||
l2d:
|
||||
@echo $(PP)
|
||||
@${SOURCE_EDA_LC}; lc_shell -f $(TCLPATH)/lib_to_db.tcl | tee lib2db.log
|
||||
|
||||
check: pt f c_R0
|
||||
|
||||
submit: l2d copy_sdc svn
|
||||
|
||||
run_all:
|
||||
$(SCRIPTPATH)/runAll.sh
|
||||
|
||||
svn: copy_sdc
|
||||
$(SCRIPTPATH)/SVNSubmit.sh
|
||||
|
||||
setPP:
|
||||
@echo $(PP)
|
||||
$(SCRIPTPATH)/setPP.sh
|
||||
@echo $(PP)
|
||||
|
||||
copy_sdc:
|
||||
@echo $(PP)
|
||||
$(SCRIPTPATH)/copy_sdc.sh
|
||||
|
||||
f:
|
||||
@${SOURCE_EDA_FM}; fm_shell -64 -f $(TCLPATH)/formality.tcl | tee fm.log ${DCWORK}/Logs/fm_${current_date}.log
|
||||
|
||||
flow : export FLOW = TRUE
|
||||
flow: syn pt submit f c_R0
|
||||
|
||||
cplib2db:
|
||||
@${SOURCE_EDA_DC}; dc_shell -f $(TCLPATH)/copyLib.tcl
|
||||
cd ../db-8024/ && lib2db.tcl
|
||||
|
||||
Prepare:
|
||||
$(SCRIPTPATH)/quick_start
|
||||
|
||||
############################
|
||||
## CLEAN
|
||||
############################
|
||||
.PHONY: simclean
|
||||
simclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf xcelium.d xrun.log xrun.key xrun.history novas_dump.log Log waves_M7004v.shm indago_logs_backup cdns_dump.log indago_logs xncsim xmvhdl.log hdl.var
|
||||
@rm -rf cds.lib error.log warn.log log .indago_auto_save .simvision synopsys_sim.setup simv waves_M7004v.fsdb .bpad Printout all_stimulation/ddr0_ini_path0.dat RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex
|
||||
|
||||
.PHONY: vcsclean
|
||||
vcsclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf simv.daidir csrc vcs_lib verdiLog novas.rc verdi_config_file novas.conf ucli.key vc_hdrs.h vcs.log RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex
|
||||
|
||||
.PHONY: synclean
|
||||
synclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf xxxxa.log dc.log pt.log formality.log fm_shell_command.log RTL_DC_info.log command.log analyzed alib-52 default.svf synopsysdc
|
||||
|
||||
.PHONY: sgclean
|
||||
sgclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf ./sypglass.work/sg_results *.out xxxxa.log
|
||||
|
||||
.PHONY: genusclean
|
||||
genusclean:
|
||||
@touch genus.log
|
||||
@rm -rf genus.*
|
||||
|
||||
.PHONY: cleanall
|
||||
cleanall:
|
||||
@rm -rf analyzed alib-52 default.svf synopsysdc xcelium.d xrun.key xrun.history Log *.shm indago_logs ./sypglass.work/sg_results *.log *.out *.shm xncsim hdl.var simv.daidir csrc vcs_lib verdiLog novas.rc verdi_config_file novas.conf ucli.key vc_hdrs.h RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex cds.lib .indago_auto_save .simvision synopsys_sim.setup simv *.fsdb .bpad Printout
|
||||
|
||||
|
||||
@ -1,440 +0,0 @@
|
||||
##---------------------------------------------------------------------
|
||||
# COPYRIGHT (C) 2020
|
||||
## This software and the associated documentation are confidential and
|
||||
## proprietary to 671.
|
||||
##
|
||||
## The entire notice above must be reproduced on all authorized copies.
|
||||
##----------------------------------------------------------------------
|
||||
SHELL := /bin/csh
|
||||
|
||||
################## DC env ###########################################
|
||||
export DCWORK = ./dc.work
|
||||
export DC_FILELIST = ${DCWORK}/filelist.v
|
||||
export PP ?= ./
|
||||
export PROJECTPATH = $(shell $(SCRIPTPATH)/get_PROJECT_PATH.sh)
|
||||
export RELATIVEPATH = /space/CAD_Front_End/Synopsys/syn/demo
|
||||
#export RELATIVEPATH = /home/admin/liuchang/FrontEnd_Flow
|
||||
export SCRIPTPATH = $(RELATIVEPATH)/Scripts
|
||||
export TCLPATH = $(RELATIVEPATH)/Tcls
|
||||
export SDCPATH = $(PROJECTPATH)/syn/SDC
|
||||
export VPATH = $(SCRIPTPATH):$(TCLPATH):$(SDCPATH)
|
||||
export FLOW ?= FALSE
|
||||
export DEBUGSDC ?= FALSE
|
||||
export LOADDDC ?= FALSE
|
||||
export CHECKTIMING ?= FALSE
|
||||
export CHECKCODE ?= FALSE
|
||||
export FLAT ?= FALSE
|
||||
export PATH = $(VPATH):$(shell echo $$PATH)
|
||||
SOURCE_EDA_DC = source /space/CAD_Front_End/Synopsys/syn/syn_S-2021.06-SP4.setup
|
||||
SOURCE_EDA_PT = source /space/CAD_Front_End/Synopsys/prime/prime_S-2021.06-SP4.setup
|
||||
SOURCE_EDA_FM = source /space/CAD_Front_End/Synopsys/fm/fm_S-2021.06-SP4.setup
|
||||
SOURCE_EDA_LC = source /space/CAD_Front_End/Synopsys2020/lc/lc_R-2020.09-SP3.setup
|
||||
#SOURCE_EDA_DC = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
|
||||
#SOURCE_EDA_PT = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
|
||||
#SOURCE_EDA_FM = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
|
||||
#SOURCE_EDA_LC = source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup
|
||||
export SNPSLMD_LICENSE_FILE = $(shell source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup && echo $$SNPSLMD_LICENSE_FILE)
|
||||
#export PATH = $(VPATH):$(shell source /space/CAD_Front_End/Synopsys2013/dc_2013.setup && source /space/CAD_Front_End/Synopsys2019/synopsys2019_setup && echo $$PATH)
|
||||
###########################################################################
|
||||
|
||||
################### Sim env ###############################################
|
||||
export NCWORK = ./nc.work
|
||||
export NC_FILELIST = ${NCWORK}/sim_filelist.f
|
||||
export DESIGN = $(shell $(SCRIPTPATH)/get_CURRENT_DESIGN.sh)
|
||||
export SIMULATOR ?= NC
|
||||
|
||||
SOURCE_EDA_xcelium = source /space/CAD_Front_End/Cadence/xcelium/xcelium_2105001.setup
|
||||
SOURCE_EDA_indago = source /space/CAD_Front_End/Cadence/indago/indago_2105001.setup
|
||||
SOURCE_EDA_vmanager= source /space/CAD_Front_End/Cadence2020/vmanager_2003.setup
|
||||
SOURCE_EDA_verdi = source /space/CAD_Front_End/Synopsys/verdi/verdi_R-2020.12.setup
|
||||
SOURCE_EDA_vcs = source /space/CAD_Front_End/Synopsys/vcs/vcs_R-2020.12.setup
|
||||
XRUN = @${SOURCE_EDA_xcelium}; xrun -sv -access rwc -lwdgen -source_debug -work work -nospecify -run -64bit -nowarn CUNGL1 -nowarn NONPRT -timescale 1ns/1ps -parseinfo include
|
||||
SV = @${SOURCE_EDA_xcelium}; simvision -64bit
|
||||
INDAGO = @${SOURCE_EDA_indago} ; indago -wave_db
|
||||
XMVHDL = @${SOURCE_EDA_xcelium} ; xmvhdl -64bit -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright
|
||||
VCS = ${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vcs -full64 -sverilog -kdb -lca +nospecify -error=noMPD -debug_acc
|
||||
VCS_F = ${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vcs -full64 -sverilog -kdb -lca +nospecify -error=noMPD
|
||||
VERDI = ${SOURCE_EDA_verdi} ; ${SOURCE_EDA_vcs} ; verdi -nologo
|
||||
IMC = ${SOURCE_EDA_vmanager} ; imc -64bit -gui
|
||||
VHDLAN = @${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vhdlan -full64 -kdb
|
||||
VLOGAN = @${SOURCE_EDA_vcs} ; ${SOURCE_EDA_verdi}; vlogan -full64 -kdb -sverilog -error=noMPD
|
||||
CDSGEN = @${SOURCE_EDA_xcelium} ; $(SCRIPTPATH)/cds_gen
|
||||
###########################################################################
|
||||
|
||||
################### Spyglass env ##########################################
|
||||
SOURCE_EDA_spyglass = source /space/CAD_Front_End/Synopsys/spyglass/spyglass_S-2021.09-SP1.setup
|
||||
export SPYGLASSWORK = ./spyglass.work
|
||||
#pre-define env variable. don't modify it
|
||||
export RUN_POWER_FLOW = no
|
||||
export RUN_CDC_FLOW = no
|
||||
export RUN_RDC_FLOW = no
|
||||
export RUN_CONSTRAINT_FLOW = no
|
||||
export RUN_TXV_FLOW = no
|
||||
#----------------------------------------
|
||||
export LINT_DONT_SET_TOP = no
|
||||
export USE_CUSTOM_METHODOLOGY = no
|
||||
export SG_CUSTOM_METHODOLOGY_DIR = $(SCRIPTPATH)/custom_methodology
|
||||
#export SG_SRC_FILELIST = src.f ????
|
||||
export SG_SRC_FILELIST = ${NC_FILELIST}
|
||||
export SG_TECH_LIBFILE = ${PROJECTPATH}/syn/spyglass_tech_lib.f
|
||||
export SG_REPORT_DIR = ${SPYGLASSWORK}/sg_results
|
||||
export top-module-name = ${DESIGN}
|
||||
###########################################################################
|
||||
|
||||
################### EasyECO env ##########################################
|
||||
SOURCE_EDA_easyECO = source /home/admin/easyeco-release-2022_04_13_17_01_32/easyECO.setup
|
||||
export ECO_COMM ?= ECO
|
||||
|
||||
###########################################################################
|
||||
|
||||
current_date = $(shell date +%Y_%m%d_%H%M)
|
||||
|
||||
lec:
|
||||
@${SOURCE_EDA_easyECO}; ./ezlec.sh
|
||||
|
||||
eco:
|
||||
@${SOURCE_EDA_easyECO}; ./ezeco.sh
|
||||
|
||||
autoeco:
|
||||
@${SOURCE_EDA_easyECO}; ${SOURCE_EDA_FM}; ./auto_eco.sh
|
||||
|
||||
help:
|
||||
@echo "###########################################################################"
|
||||
@echo " -------"
|
||||
@echo " | |"
|
||||
@echo " | * * |"
|
||||
@echo " | ? |"
|
||||
@echo " | |"
|
||||
@echo " | (_) |"
|
||||
@echo " ---------"
|
||||
@echo ""
|
||||
@echo "If encountering problems during use, please checking the following:"
|
||||
@echo "Checking ProjectPathSetting.tcl."
|
||||
@echo "Checking filelist.v."
|
||||
@echo "Checking setModuleName.tcl."
|
||||
@echo "Checking RELATIVEPATH in Makefile."
|
||||
@echo "Checking syn_specific.tcl."
|
||||
@echo "Checking synopsys_dc.setup."
|
||||
@echo "Checking whether all linked library are in the *db* folder."
|
||||
@echo ""
|
||||
@echo "SYNTAX"
|
||||
@echo " make"
|
||||
@echo " [Prepare] : Create a working environment."
|
||||
@echo " [clean] : Clean all temporary files."
|
||||
@echo " [help] : make help."
|
||||
@echo " [xrun] : Start the NC tool for simulation."
|
||||
@echo " [xrun_nogui] : Start the NC tool for simulation without gui."
|
||||
@echo " [indago] : Start the indago tool for debugging."
|
||||
@echo " [sim] : Same as make xrun."
|
||||
@echo " [design_audit] : Check spyglass running environment."
|
||||
@echo " [lint] : Start the spyglass tool for checking lint."
|
||||
@echo " [cdc] : Start the spyglass tool for checking cdc."
|
||||
@echo " [code_check_all] : Check whether the code meets the submission requirements."
|
||||
@echo " [c_k] : make check_warning, find all warnings"
|
||||
@echo " [c_e] : make check_error, find all errors in dc.log"
|
||||
@echo " [c_R0] [PP=*] : R0 check in dc.log, pt.log, fm.log, need to give check path, default ./ ."
|
||||
@echo " [pt] [PP=*] : make pt, generate check_timing_pt.txt and .lib, need to give check path, default ./ ."
|
||||
@echo " [l2d] [PP=*] : make lib2db, need to give check path, default ./ ."
|
||||
@echo " [check][PP=*] : make c_R0, pt and fomality, need to give check path, default ./ ."
|
||||
@echo " [svn] [PP=*] : copy submit files into Netlist, and svn commit. need to give check path, default ./ ."
|
||||
@echo " [submit] [PP=*] : l2d, copy_sdc, svn. need to give check path, default ./ ."
|
||||
@echo " [f] [PP=*] : make fomality, need to give check path, default ./ ."
|
||||
@echo " [syn] : make synthesize, use syn_main.tcl, "
|
||||
@echo " [flow] : make syn, check, and submit."
|
||||
@echo " [gen_fl] : generate the filelist of current module."
|
||||
@echo " [tab_c] : check the tab in RTL code, and change it into n space."
|
||||
@echo "#################################################"
|
||||
|
||||
######################################################################
|
||||
# Sim
|
||||
######################################################################
|
||||
begin: simclean
|
||||
@echo "=============compiling ft-m7004 rtl codes=============="
|
||||
@echo "NOTE: current code source path is: " ${PROJECTPATH}" "
|
||||
ln -snf ${PROJECTPATH}/src/BOOT/rtl/RBL_512w128b_ROM1.hex RBL_512w128b_ROM1.hex
|
||||
ln -snf ${PROJECTPATH}/src/BOOT/rtl/RBL_512w128b_ROM2.hex RBL_512w128b_ROM2.hex
|
||||
|
||||
compile_vhd: cds
|
||||
./nc.work/sim_specific.sh ${SIMULATOR}
|
||||
|
||||
xrun: begin compile_vhd
|
||||
@${XRUN} -gui -top ${DESIGN} -define _SIMULATION_ -f ${NC_FILELIST}
|
||||
|
||||
xrun_nogui: begin compile_vhd
|
||||
@${XRUN} -top ${DESIGN} -define _SIMULATION_ -exit -f ${NC_FILELIST}
|
||||
|
||||
vcs: export SIMULATOR = VCS
|
||||
vcs: begin compile_vhd
|
||||
@${VLOGAN} -f ${NC_FILELIST} +define+_SIMULATION_ | tee vcs.log
|
||||
@${VCS} -top ${DESIGN} -R | tee -a vcs.log
|
||||
|
||||
vcsfast:begin_vcs
|
||||
@${VLOGAN} -f ${NC_FILELIST} | tee vcs.log
|
||||
@${VCS_F} -top ${DESIGN} -R | tee -a vcs.log
|
||||
|
||||
sv:
|
||||
@${SV}
|
||||
|
||||
indago:
|
||||
@${INDAGO} ${DESIGN}.shm
|
||||
|
||||
sim: xrun_nogui
|
||||
|
||||
|
||||
#verdinet: export NOVAS_LIBS="/home/admin/liuchang/M7004V/syn/db/RHSTD_LVT_ssg0p72vm40c_ccs.lib /home/admin/liuchang/M7004V/syn/db/RHSTD_RVT_ssg0p72vm40c_ccs.lib"
|
||||
#@${VERDI} -novasLibs "RHSTD_LVT_ssg0p72vm40c_ccs.lib++ RHSTD_RVT_ssg0p72vm40c_ccs.lib++" -dbdir simv.daidir
|
||||
|
||||
verdinet:
|
||||
@${VLOGAN} -f ${NC_FILELIST} $(PP)/result/${DESIGN}.sv +define+_SIMULATION_ | tee vcs.log
|
||||
@${VCS_F} -top ${DESIGN} | tee -a vcs.log
|
||||
@${VERDI} -dbdir simv.daidir
|
||||
|
||||
verdi:
|
||||
@${VERDI} -ssf ${DESIGN}.fsdb
|
||||
|
||||
cds:
|
||||
@${CDSGEN}
|
||||
|
||||
######################################################################
|
||||
# Spyglass
|
||||
######################################################################
|
||||
#setup:
|
||||
# ln -snf /space/CAD_Front_End/Synopsys/spyglass/pdf/lint/spyglass_lint_reference_manul_gfkdwdzs_V1.pdf spyglass_lint_reference.pdf
|
||||
# mv ethmac.prj ${top-module-name}.prj
|
||||
# mv waiver/ethmac.awl waiver/${top-module-name}.awl
|
||||
|
||||
link_spyglass_reference:
|
||||
ln -snf /space/CAD_Front_End/Synopsys/spyglass/pdf/lint/spyglass_lint_reference_manul_gfkdwdzs_V1.pdf spyglass_lint_Error_Warning_reference.pdf
|
||||
|
||||
design_audit:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal lint/design_audit
|
||||
gvim ${SG_REPORT_DIR}/${top-module-name}/consolidated_reports/${top-module-name}_lint_design_audit/Audit.rpt
|
||||
|
||||
lint: link_spyglass_reference
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal lint/lint_rtl
|
||||
|
||||
#gvim ${SG_REPORT_DIR}/${top-module-name}/consolidated_reports/${top-module-name}_lint_lint_rtl/moresimple.rpt
|
||||
|
||||
cdc: cdc_setup_check clock_reset_integrity cdc_verify_struct
|
||||
|
||||
cdc_setup:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_setup
|
||||
@echo "=========INFO: SpyGlass would automatically extract design clock/reset constraint ==========="
|
||||
@echo "=========INFO: User can refer to below files and modify the clock domain as required ==========="
|
||||
@echo "=========INFO: Then user can add the refined cosntraints in the top design sgdc file ==========="
|
||||
@echo "egrep \"^clock\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/autoclocks.sgdc"
|
||||
@echo "egrep \"^clock\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/generated_clocks.sgdc"
|
||||
@echo "egrep \"^reset\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/autoresets.sgdc"
|
||||
@echo "egrep \"^reset\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/generated_resets.sgdc"
|
||||
@echo "egrep \"^set_case_analysis\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup/spyglass_reports/clock-reset/auto_case_analysis.sgdc"
|
||||
cdc_setup_check:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_setup_check
|
||||
@echo "=========INFO: If there were any unconstraint primary ports and bbox ==========="
|
||||
@echo "=========INFO: SpyGlass would automatically generate a template cdc constriant for them ==========="
|
||||
@echo "=========INFO: User can refer to below two files and modify related port clock as required ==========="
|
||||
@echo "=========INFO: Then user can add the refined cosntraints in the top design sgdc file ==========="
|
||||
@echo "egrep \"^abstract_port\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup_check/spyglass_reports/clock-reset/${top-module-name}_input_abstract.sgdc"
|
||||
@echo "egrep \"^abstract_port\" ${SG_REPORT_DIR}/${top-module-name}/${top-module-name}/cdc/cdc_setup_check/spyglass_reports/clock-reset/Setup_blackbox01/${top-module-name}_bbox_model.sgdc"
|
||||
clock_reset_integrity:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/clock_reset_integrity
|
||||
cdc_verify_struct:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_verify_struct
|
||||
cdc_verify:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal cdc/cdc_verify
|
||||
rdc:
|
||||
export RUN_RDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal rdc/rdc_verify_struct
|
||||
power_audit:
|
||||
export RUN_POWER_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_audit
|
||||
power_activity_check:
|
||||
export RUN_POWER_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_activity_check
|
||||
power_est_profiling:
|
||||
export RUN_POWER_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_est_profiling
|
||||
power_cge_profiling:
|
||||
export RUN_POWER_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_cge_profiling
|
||||
power: export RUN_POWER_FLOW = yes
|
||||
power:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal power/power_audit,power/power_activity_check,power/power_est_profiling
|
||||
exec mkdir ./spyglass.work/${top-module-name}_${current_date}
|
||||
exec cp -r ./spyglass.work/sg_results/${top-module-name}/consolidated_reports/* ./spyglass.work/${top-module-name}_${current_date}/
|
||||
sdc_gen:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_gen
|
||||
sdc_audit:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_audit
|
||||
sdc_check:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_check
|
||||
sdc_exception_struct:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_exception_struct
|
||||
sdc_redundancy:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_redundancy
|
||||
sdc_equiv:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_equiv
|
||||
sdc_hier_equiv:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_hier_equiv
|
||||
sdc:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal constraints/sdc_audit,constraints/sdc_check,constraints/sdc_exception_struct,constraints/sdc_redundancy
|
||||
fp_verification:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/fp_verification
|
||||
mcp_verification:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/mcp_verification
|
||||
txv:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj -batch -goal txv_verification/fp_mcp_verification
|
||||
|
||||
lintgui:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
cdcgui:
|
||||
export RUN_CDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
|
||||
rdcgui:
|
||||
export RUN_RDC_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
sdcgui:
|
||||
export RUN_CONSTRAINT_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
txvgui:
|
||||
export RUN_TXV_FLOW=yes;\
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
powergui: export RUN_POWER_FLOW = yes
|
||||
powergui:
|
||||
@${SOURCE_EDA_spyglass}; spyglass -project ${SPYGLASSWORK}/${top-module-name}.prj &
|
||||
|
||||
######################################################################
|
||||
# Genus
|
||||
######################################################################
|
||||
genus : genusclean
|
||||
@/space/CAD_Back_End/Cadence20/GENUS201/bin/genus -file $(TCLPATH)/genus_flow.tcl
|
||||
|
||||
######################################################################
|
||||
# DC, PT & FM
|
||||
######################################################################
|
||||
syn : synclean c_SRC_ID Prepare
|
||||
@${SOURCE_EDA_DC}; dc_shell-t -f $(TCLPATH)/syn_main.tcl | tee dc.log ${DCWORK}/Logs/dc_${current_date}.log
|
||||
|
||||
get_DBs_info:
|
||||
$(SCRIPTPATH)/get_DBs_info.sh
|
||||
|
||||
report_dc_summary:
|
||||
$(SCRIPTPATH)/report_dc_summary.sh
|
||||
|
||||
c_w:
|
||||
$(SCRIPTPATH)/warning_find.perl
|
||||
|
||||
c_e:
|
||||
$(SCRIPTPATH)/error_find.perl
|
||||
|
||||
code_check_all: CHECKCODE = TRUE
|
||||
code_check_all: c_SRC_ID sim syn lint
|
||||
$(SCRIPTPATH)/check_code.sh
|
||||
gvim code_check.result
|
||||
|
||||
code_check:
|
||||
$(SCRIPTPATH)/check_code.sh
|
||||
gvim code_check.result
|
||||
|
||||
c_SRC_ID:
|
||||
$(SCRIPTPATH)/check_SRC_ID.sh
|
||||
|
||||
c_R0:
|
||||
$(SCRIPTPATH)/check_R0.sh
|
||||
|
||||
gen_fl:
|
||||
$(SCRIPTPATH)/filelist_gen.sh
|
||||
|
||||
tab_c:
|
||||
$(SCRIPTPATH)/tab_change
|
||||
|
||||
pt: Prepare
|
||||
@${SOURCE_EDA_PT}; pt_shell -f $(TCLPATH)/pt.tcl | tee pt.log pt_${current_date}.log
|
||||
mv pt_${current_date}.log ${DCWORK}/Logs
|
||||
|
||||
l2d:
|
||||
@echo $(PP)
|
||||
@${SOURCE_EDA_LC}; lc_shell -f $(TCLPATH)/lib_to_db.tcl | tee lib2db.log
|
||||
|
||||
check: pt f c_R0
|
||||
|
||||
submit: l2d copy_sdc svn
|
||||
|
||||
run_all:
|
||||
$(SCRIPTPATH)/runAll.sh
|
||||
|
||||
svn: copy_sdc
|
||||
$(SCRIPTPATH)/SVNSubmit.sh
|
||||
|
||||
setPP:
|
||||
@echo $(PP)
|
||||
$(SCRIPTPATH)/setPP.sh
|
||||
@echo $(PP)
|
||||
|
||||
copy_sdc:
|
||||
@echo $(PP)
|
||||
$(SCRIPTPATH)/copy_sdc.sh
|
||||
|
||||
f:
|
||||
@${SOURCE_EDA_FM}; fm_shell -64 -f $(TCLPATH)/formality.tcl | tee fm.log ${DCWORK}/Logs/fm_${current_date}.log
|
||||
|
||||
flow : export FLOW = TRUE
|
||||
flow: syn pt submit f c_R0
|
||||
|
||||
cplib2db:
|
||||
@${SOURCE_EDA_DC}; dc_shell -f $(TCLPATH)/copyLib.tcl
|
||||
cd ../db-8024/ && lib2db.tcl
|
||||
|
||||
Prepare:
|
||||
$(SCRIPTPATH)/quick_start
|
||||
|
||||
############################
|
||||
## CLEAN
|
||||
############################
|
||||
.PHONY: simclean
|
||||
simclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf xcelium.d xrun.log xrun.key xrun.history novas_dump.log Log waves_M7004v.shm indago_logs_backup cdns_dump.log indago_logs xncsim xmvhdl.log hdl.var
|
||||
@rm -rf cds.lib error.log warn.log log .indago_auto_save .simvision synopsys_sim.setup simv waves_M7004v.fsdb .bpad Printout all_stimulation/ddr0_ini_path0.dat RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex
|
||||
|
||||
.PHONY: vcsclean
|
||||
vcsclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf simv.daidir csrc vcs_lib verdiLog novas.rc verdi_config_file novas.conf ucli.key vc_hdrs.h vcs.log RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex
|
||||
|
||||
.PHONY: synclean
|
||||
synclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf xxxxa.log dc.log pt.log formality.log fm_shell_command.log RTL_DC_info.log command.log analyzed alib-52 default.svf synopsysdc
|
||||
|
||||
.PHONY: sgclean
|
||||
sgclean:
|
||||
@touch xxxxa.log
|
||||
@rm -rf ./sypglass.work/sg_results *.out xxxxa.log
|
||||
|
||||
.PHONY: genusclean
|
||||
genusclean:
|
||||
@touch genus.log
|
||||
@rm -rf genus.*
|
||||
|
||||
.PHONY: cleanall
|
||||
cleanall:
|
||||
@rm -rf analyzed alib-52 default.svf synopsysdc xcelium.d xrun.key xrun.history Log *.shm indago_logs ./sypglass.work/sg_results *.log *.out *.shm xncsim hdl.var simv.daidir csrc vcs_lib verdiLog novas.rc verdi_config_file novas.conf ucli.key vc_hdrs.h RBL_512w128b_ROM1.hex RBL_512w128b_ROM2.hex cds.lib .indago_auto_save .simvision synopsys_sim.setup simv *.fsdb .bpad Printout
|
||||
|
||||
|
||||
@ -1,2 +0,0 @@
|
||||
set PROJECTPATH /home/UWE/zj/cv32e40p-master
|
||||
puts ${PROJECTPATH}
|
||||
@ -1,7 +0,0 @@
|
||||
Checking dc.log ...
|
||||
|
||||
Checking check_timing.txt and check_design.txt ...
|
||||
|
||||
Checking pt.log, check_timing_pt.txt ...
|
||||
|
||||
Checking fm.log ...
|
||||
@ -1,30 +0,0 @@
|
||||
dir=`tclsh ./ProjectPathSetting.tcl`
|
||||
moduleName=`tclsh setModuleName.tcl`
|
||||
echo $dir
|
||||
echo $moduleName
|
||||
netlistpath=`find $dir -name '*Netlist' -type d`
|
||||
echo $netlistpath
|
||||
|
||||
if [ -d $netlistpath/${moduleName} ]; then
|
||||
rm -r $netlistpath/${moduleName}
|
||||
echo "remove $netlistpath/${moduleName}"
|
||||
fi
|
||||
|
||||
mkdir $netlistpath/${moduleName}
|
||||
|
||||
PP=`setPP.sh`
|
||||
echo "PP = ${PP}"
|
||||
PP_date=${PP#*dc.work/}
|
||||
echo "PP_date = ${PP#*dc.work/}"
|
||||
|
||||
cp {${PP}/result/*.db,${PP}/result/*.lib,${PP}/RTL_DC_info.log} NetlistSubmit/${PP_date}/
|
||||
cp ./NetlistSubmit/${PP_date}/*.db ../../db*
|
||||
cp ./NetlistSubmit/${PP_date}/*.sv ../../db*
|
||||
cp -r ./NetlistSubmit/${PP_date}/* $netlistpath/${moduleName}/
|
||||
|
||||
cd $netlistpath
|
||||
#svn up
|
||||
#svn add ${moduleName}/*
|
||||
#echo "svn add $netlistpath/${moduleName}"
|
||||
echo "svn ci $netlistpath/${moduleName}"
|
||||
svn ci -m "${PP}" ${moduleName}/
|
||||
@ -1,85 +0,0 @@
|
||||
moduleName=`tclsh setModuleName.tcl`
|
||||
echo $moduleName
|
||||
|
||||
PP=`setPP.sh`
|
||||
echo "PP = ${PP}"
|
||||
|
||||
while read line
|
||||
do
|
||||
echo $line
|
||||
R1_PATH=`echo $line`
|
||||
echo $R1_PATH
|
||||
done < dc.work/R1_PATH.txt
|
||||
|
||||
while read line
|
||||
do
|
||||
echo $line
|
||||
LAST_ECO=`echo $line`
|
||||
echo $LAST_ECO
|
||||
done < ez.work/LastECO.txt
|
||||
|
||||
echo $ECO_COMM
|
||||
if [ -d ./ez.work/$ECO_COMM ]; then
|
||||
echo "$ECO_COMM already exist"
|
||||
exit
|
||||
#rm -r ./ez.work/$ECO_COMM
|
||||
fi
|
||||
mkdir ez.work/$ECO_COMM
|
||||
|
||||
ls /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/Memory/V2P4/memory_lib_dbs/ssgs_ccw0p72vn40c/*.lib > ez.work/lib.f
|
||||
ls /space/PRJ_Front_End/M7004V/src/DSPCORE/VRF/lib/*WC.lib >> ez.work/lib.f
|
||||
ls /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/LVT/lib/RHSTD_LVT_ssg0p72vm40c_ccs.lib >> ez.work/lib.f
|
||||
|
||||
cp ${PROJECTPATH}/syn/dont_use.tcl ez.work/dont_use_cells.tcl
|
||||
sed -i "s?set_dont_use?dont_use_cell?" ez.work/dont_use_cells.tcl
|
||||
|
||||
${SCRIPTPATH}/ezeco_setup.sh dc
|
||||
|
||||
${SCRIPTPATH}/ezlec.sh
|
||||
|
||||
ezeco -in ./ez.work/$ECO_COMM/easyeco_setup.script -rtl_eco_info ./ez.work/$ECO_COMM/eco_module_info.txt
|
||||
|
||||
cp ez.work/$ECO_COMM/${moduleName}_eco.sv.v $R1_PATH/result/${moduleName}_eco.sv
|
||||
|
||||
cp ${TCLPATH}/formality.tcl ez.work/$ECO_COMM/
|
||||
|
||||
fm_eco_to_svf ./ez.work/R1src/rtl ./src/rtl > ./ez.work/$ECO_COMM/eco_change.svf
|
||||
|
||||
sed -i 's?./${PP}/result/${Design}.sv?./${R1_PATH}/result/${Design}_eco.sv?' ez.work/$ECO_COMM/formality.tcl
|
||||
sed -i 's?./${PP}/report/$Design.svf?./${R1_PATH}/report/$Design.svf?' ez.work/$ECO_COMM/formality.tcl
|
||||
sed -i "s?Design.svf?Design.svf ./ez.work/$ECO_COMM/eco_change.svf?" ez.work/$ECO_COMM/formality.tcl
|
||||
sed -i "s?fm.log?fm_ez.log?" ez.work/$ECO_COMM/formality.tcl
|
||||
sed -i "s?fm_svf?fm_ez_svf?" ez.work/$ECO_COMM/formality.tcl
|
||||
|
||||
fm_shell -64 -f ./ez.work/$ECO_COMM/formality.tcl | tee fm_ez.log ${DCWORK}/Logs/fm_ez_${current_date}.log
|
||||
|
||||
fm_result=`grep "Verification SUCCEEDED" fm_ez.log`
|
||||
if [[ ${fm_result} == "" ]]; then
|
||||
echo "ECO FM CHECK FAILED!!!"
|
||||
exit
|
||||
else
|
||||
echo "ECO FM CHECK SUCCEEDED!"
|
||||
fi
|
||||
|
||||
${SCRIPTPATH}/ezeco_setup.sh dft
|
||||
|
||||
ezeco -in ./ez.work/$ECO_COMM/easyeco_dft_setup.script -rtl_eco_info ./ez.work/$ECO_COMM/eco_module_info.txt
|
||||
|
||||
cp ez.work/$ECO_COMM/${moduleName}_dft_eco.sv.v $R1_PATH/result/${moduleName}_dft_eco.v
|
||||
|
||||
#ls /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/RVT/lib/RHSTD_RVT_ssg0p72vm40c_ccs.lib >> ez.work/lib.f
|
||||
#ls /space/PRJ_Front_End/M7004V/hardmacro_backend/ip/CoreLib/Latest/ULVT/lib/RHSTD_ULVT_ssg0p72vm40c_ccs.lib >> ez.work/lib.f
|
||||
#
|
||||
#${SCRIPTPATH}/ezeco_setup.sh pr
|
||||
#
|
||||
#ezeco -in ./ez.work/$ECO_COMM/easyeco_pr_setup.script -rtl_eco_info ./ez.work/$ECO_COMM/eco_module_info.txt
|
||||
#
|
||||
#cp ez.work/$ECO_COMM/${moduleName}_pr_eco.sv.v $R1_PATH/result/${moduleName}_pr_eco.v
|
||||
|
||||
#if [ -e $R1_PATH/result/${moduleName}.v ]; then
|
||||
# mv $R1_PATH/result/${moduleName}.v $R1_PATH/result/${moduleName}_B4_$ECO_COMM.v
|
||||
#else
|
||||
# mv $R1_PATH/result/${moduleName}.sv $R1_PATH/result/${moduleName}_B4_$ECO_COMM.sv
|
||||
#fi
|
||||
|
||||
echo ez.work/$ECO_COMM > ez.work/LastECO.txt
|
||||
@ -1,14 +0,0 @@
|
||||
echo "FullChip"; grep "_D_" ./Syn_FullChip/20190418_1124/result/DM6672V_FullChip_20190418_1124_ultra.v | wc -l
|
||||
echo "VPIF"; grep "_D_" ./Syn_SubModule/Syn_VPIF/20190408_0916/result/*.v | wc -l
|
||||
echo "GMAC"; grep "_D_" ./Syn_SubModule/Syn_GMAC/20190108_1644/result/*.v | wc -l
|
||||
echo "DDR"; grep "_D_" ./Syn_SubModule/Syn_DDR/20190108_1644/result/*.v | wc -l
|
||||
echo "H264E"; grep "_D_" ./Syn_SubModule/Syn_H264E/20190108_1644/result/*.v | wc -l
|
||||
echo "CD"; grep "_D_" ./Syn_SubModule/Syn_CrossNet_Data/20190407_2037/result/*.v | wc -l
|
||||
echo "CC"; grep "_D_" ./Syn_SubModule/Syn_CrossNet_Config/20190407_2037/result/*.v | wc -l
|
||||
echo "SMC_BankPort"; grep "_D_" ./Syn_SubModule/Syn_SMC_BankPort/20190108_1644/result/*.v | wc -l
|
||||
echo "CorePac"; grep "_D_" ./Syn_SubModule/Syn_CorePac/*.v | wc -l
|
||||
echo "H264D"; grep "_D_" ./Syn_SubModule/Syn_H264D/20190108_1644/result/*.v | wc -l
|
||||
echo "SMC"; grep "_D_" ./Syn_SubModule/Syn_SMC/20190108_1708/result/*.v | wc -l
|
||||
echo "DMAx"; grep "_D_" ./Syn_SubModule/Syn_DMAx/20190108_1644/result/*.v | wc -l
|
||||
echo "PPC"; grep "_D_" ./Syn_SubModule/Syn_PowerPC/20190108_1644/result/*.v | wc -l
|
||||
echo "SRIO"; grep "_D_" ./Syn_SubModule/Syn_SRIO/20190226_0837/result/*.v | wc -l
|
||||
@ -1,26 +0,0 @@
|
||||
#!/bin/sh
|
||||
#Author: liusheng
|
||||
#Date: 2019.09.03
|
||||
#Role: use it, users do not need to modify the path in cds.lib.
|
||||
|
||||
|
||||
NC_PATH=`which simvision`
|
||||
|
||||
CDS_LIB_PATH=${NC_PATH/\/bin\/simvision/.lnx86\/inca\/files\/cds.lib}
|
||||
|
||||
echo "# Contain a project-wide cds.lib" > cds.lib
|
||||
echo INCLUDE ${CDS_LIB_PATH} >> cds.lib
|
||||
echo " " >> cds.lib
|
||||
echo "# Bind library. Logic name <=> Physical Library path." >> cds.lib
|
||||
echo "# ======LEON3's Library=====" >> cds.lib
|
||||
echo "DEFINE grlib xncsim/grlib" >> cds.lib
|
||||
echo "DEFINE techmap xncsim/techmap" >> cds.lib
|
||||
echo "DEFINE gaisler xncsim/gaisler" >> cds.lib
|
||||
echo "DEFINE work xncsim/work" >> cds.lib
|
||||
|
||||
echo "WORK > DEFAULT" > synopsys_sim.setup
|
||||
echo "DEFAULT:vcs_lib/work" >> synopsys_sim.setup
|
||||
echo "grlib:vcs_lib/grlib" >> synopsys_sim.setup
|
||||
echo "gaisler:vcs_lib/gaisler" >> synopsys_sim.setup
|
||||
echo "techmap:vcs_lib/techmap" >> synopsys_sim.setup
|
||||
|
||||
@ -1,11 +0,0 @@
|
||||
find . -name "log.txt" | xargs grep "Error:" > check.result
|
||||
find . -name "log.txt" | xargs grep "Can't" >> check.result
|
||||
find . -name "log.txt" | xargs grep "unresolv" >> check.result
|
||||
find . -name "fm.log" | xargs grep "Error:" >> check.result
|
||||
find . -name "fm.log" | xargs grep "Can't" >> check.result
|
||||
find . -name "pt.log" | xargs grep "Error:" >> check.result
|
||||
find . -name "pt.log" | xargs grep "Can't" >> check.result
|
||||
find . -name "lib2db.log" | xargs grep "Error:" >> check.result
|
||||
find . -name "lib2db.log" | xargs grep "Can't" >> check.result
|
||||
|
||||
|
||||
@ -1,65 +0,0 @@
|
||||
PP=`./Scripts/setPP.sh`
|
||||
echo "PP = ${PP}"
|
||||
|
||||
echo "Checking dc.log ..." > R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "Error:" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "Latch " >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "Timing loop" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "FFGEN" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "have the default net type" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "unresolved" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "unmapped" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "(LINT-5)" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "sensiti" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "MV-038" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "MV-039" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "MV-513" >> R0_check.result
|
||||
find ${PP} -name "dc.log" | xargs grep "MV-514" >> R0_check.result
|
||||
|
||||
echo " " >> R0_check.result
|
||||
echo "Checking check_timing.txt and check_design.txt ..." >> R0_check.result
|
||||
find ${PP} -name "check_timing.txt" | xargs grep "timing loop" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-0)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-3)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-4)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-6)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-7)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-11)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-12)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-20)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-21)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-22)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-23)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-26)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-27)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-40)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-41)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-42)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-56)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-57)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-58)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-59)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-61)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-62)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-63)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-64)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-65)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-66)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-68)" >> R0_check.result
|
||||
find ${PP} -name "check_design.txt" | xargs grep "(LINT-69)" >> R0_check.result
|
||||
|
||||
echo " " >> R0_check.result
|
||||
echo "Checking pt.log, check_timing_pt.txt ..." >> R0_check.result
|
||||
find ${PP} -name "pt.log" | xargs grep "Error:" >> R0_check.result
|
||||
find ${PP} -name "pt.log" | xargs grep "(LNT-005)" >> R0_check.result
|
||||
find ${PP} -name "check_timing_pt.txt" | xargs grep "Error:" >> R0_check.result
|
||||
find ${PP} -name "check_timing_pt.txt" | xargs grep "Warning:" >> R0_check.result
|
||||
|
||||
echo " " >> R0_check.result
|
||||
echo "Checking fm.log ..." >> R0_check.result
|
||||
find ${PP} -name "fm.log" | xargs grep "Error: " >> R0_check.result
|
||||
find ${PP} -name "fm.log" | xargs grep "***** Verification Results *****" >> R0_check.result
|
||||
find ${PP} -name "fm.log" | xargs grep "Verification SUCCEEDED" >> R0_check.result
|
||||
find ${PP} -name "fm.log" | xargs grep "Verification FAILED" >> R0_check.result
|
||||
|
||||
cp R0_check.result ${PP}/R0_check.result
|
||||
@ -1,44 +0,0 @@
|
||||
dir=`tclsh ./ProjectPathSetting.tcl`
|
||||
moduleName=`tclsh setModuleName.tcl`
|
||||
cur_dir=`pwd`
|
||||
echo $dir
|
||||
echo $cur_dir
|
||||
echo $moduleName
|
||||
srcpath=`find $dir -maxdepth 1 -name '*src' -type d`
|
||||
echo $srcpath
|
||||
|
||||
cd src
|
||||
svn info > $cur_dir/RTL_DC_info.log
|
||||
svn list -vR >> $cur_dir/RTL_DC_info.log
|
||||
ID=`svn list -vR | cksum | awk '{print $1}'`
|
||||
echo "set RTL_DC_ID $ID" > $cur_dir/RTL_DC_ID.tcl
|
||||
|
||||
cd $cur_dir
|
||||
echo "#!/bin/sh" > update_RTL_SVN.sh
|
||||
echo "" >> update_RTL_SVN.sh
|
||||
while read line
|
||||
do
|
||||
#echo $line
|
||||
r=`echo $line | cut -d' ' -f1`
|
||||
f=`echo $line | cut -d' ' -f7`
|
||||
if [ -n "$f" ]&&[ $r != "Last" ]; then
|
||||
echo svn up -r$r $f >> update_RTL_SVN.sh
|
||||
fi
|
||||
done < RTL_DC_info.log
|
||||
|
||||
cd $srcpath/PUBLIC
|
||||
svn list -vR >> $cur_dir/RTL_DC_info.log
|
||||
svn list -vR > $cur_dir/tmp.log
|
||||
|
||||
cd $cur_dir
|
||||
while read line
|
||||
do
|
||||
#echo $line
|
||||
r=`echo $line | cut -d' ' -f1`
|
||||
f=`echo $line | cut -d' ' -f7`
|
||||
if [ -n "$f" ]&&[ $r != "Last" ]; then
|
||||
echo svn up -r$r $srcpath/PUBLIC/$f >> update_RTL_SVN.sh
|
||||
fi
|
||||
done < tmp.log
|
||||
|
||||
rm tmp.log
|
||||
@ -1,6 +0,0 @@
|
||||
#!/bin/bash
|
||||
PROJECTPATH=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl`
|
||||
find $PROJECTPATH -name "*.v" | xargs grep -n 'full_case'
|
||||
find $PROJECTPATH -name "*.v" | xargs grep -n 'parallel_case'
|
||||
find $PROJECTPATH -name "*.v" | xargs grep -n 'translate on'
|
||||
find $PROJECTPATH -name "*.v" | xargs grep -n 'translate off'
|
||||
@ -1,75 +0,0 @@
|
||||
c_date=`date +%Y_%m%d_%H%M`
|
||||
|
||||
echo "Checking filelist.v ..." > code_check.result
|
||||
filelistpath=`find ./src/ -name '*flist*' -type f`
|
||||
echo "filelistpath:" $filelistpath
|
||||
for file in $filelistpath; do
|
||||
filelistname+=${file#*src/}' '
|
||||
done
|
||||
echo "filelistname:" $filelistname
|
||||
if [ -z "$filelistname" ]; then
|
||||
echo "Error: Filelist is not exist or the name is not matching '*_filelist' format. exit."
|
||||
echo "Error: Filelist is not exist or the name is not matching '*_filelist' format. exit." >> code_check.result
|
||||
exit
|
||||
fi
|
||||
SIMEMU=`grep -n "_SIMULATION_\|_EMULATION_" $filelistpath`
|
||||
if [ -z "$SIMEMU" ]; then
|
||||
echo "Info: There are no _SIMULATION_ or _EMULATION_ definition in file $filelistname ."
|
||||
fi
|
||||
|
||||
echo " " >> code_check.result
|
||||
echo "Checking 'timescale' in *.v files ... (Warning)" >> code_check.result
|
||||
find ./src/ -name "*.v" | xargs grep -n 'timescale' >> code_check.result
|
||||
|
||||
echo " " >> code_check.result
|
||||
echo "Checking Chinese words in *.v files .. (Warning)." >> code_check.result
|
||||
find ./src/ -name "*.v" | xargs grep -nP '[\p{Han}]' >> code_check.result
|
||||
|
||||
echo " " >> code_check.result
|
||||
echo "Checking Synophsis key words in *.v files ... (Info)" >> code_check.result
|
||||
find ./src/ -name "*.v" | xargs grep -n 'full_case' >> code_check.result
|
||||
find ./src/ -name "*.v" | xargs grep -n 'parallel_case' >> code_check.result
|
||||
find ./src/ -name "*.v" | xargs grep -n 'translate on' >> code_check.result
|
||||
find ./src/ -name "*.v" | xargs grep -n 'translate off' >> code_check.result
|
||||
|
||||
echo " " >> code_check.result
|
||||
echo "Checking author notes in *.v files .. (Warning)." >> code_check.result
|
||||
for file in `find ./src/ -regex ".*\.vh\|.*\.v\|.*\.h"`
|
||||
do
|
||||
authorname=`grep -n "author\|Author\|AUTHOR\|Generated by\|created" $file`
|
||||
if [ -z "$authorname" ]; then
|
||||
echo "Warning: Author notes is not exist or the name is not matching 'author|Author|AUTHOR|Generated by|created' format in file $file"
|
||||
echo "Warning: Author notes is not exist or the name is not matching 'author|Author|AUTHOR|Generated by|created' format in file $file" >> code_check.result
|
||||
fi
|
||||
done
|
||||
|
||||
echo " " >> code_check.result
|
||||
echo "Checking NC log in xrun.log ... " >> code_check.result
|
||||
find . -maxdepth 1 -name "xrun.log" | xargs grep "*E" >> code_check.result
|
||||
find . -maxdepth 1 -name "xrun.log" | xargs grep "*W,RECOME" >> code_check.result
|
||||
find . -maxdepth 1 -name "xrun.log" | xargs grep "*W,CUVWSP" >> code_check.result
|
||||
find . -maxdepth 1 -name "xrun.log" | xargs grep "*W,CUVWSI" >> code_check.result
|
||||
find . -maxdepth 1 -name "xrun.log" | xargs grep "*W,CUVMPW" >> code_check.result
|
||||
|
||||
echo " " >> code_check.result
|
||||
echo "Checking DC dc.log ..." >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "Error:" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "Latch " >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "Timing loop" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "FFGEN" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "have the default net type" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "unresolved" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "unmapped" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "(LINT-5)" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "sensiti" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "MV-038" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "MV-039" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "MV-513" >> code_check.result
|
||||
find . -maxdepth 1 -name "dc.log" | xargs grep "MV-514" >> code_check.result
|
||||
|
||||
echo " " >> code_check.result
|
||||
echo "Checking SpyGlass Lint. ..." >> code_check.result
|
||||
find ./spyglass.work/sg_results/*/consolidated_reports/ -name "moresimple.rpt" | xargs grep "Error" >> code_check.result
|
||||
find ./spyglass.work/sg_results/*/consolidated_reports/ -name "moresimple.rpt" | xargs grep "WARNING" >> code_check.result
|
||||
|
||||
cp code_check.result Logs/code_check_${c_date}.result
|
||||
@ -1,108 +0,0 @@
|
||||
MODULES=(DDR_top PCIE_Top RapidIO_top DMA0_wrapper RA14S_top SMC_BankMem)
|
||||
MASK=( 1 1 1 1 0 1)
|
||||
|
||||
i=0
|
||||
for m in ${MODULES[@]}
|
||||
do
|
||||
echo $i ${MASK[$i]}
|
||||
if [ ${MASK[$i]} == 1 ]; then
|
||||
echo $m
|
||||
if [ $m == SMC_BankMem ]; then
|
||||
gnome-terminal --geometry=100x30+100*$i+0 --window --title="$m" -x csh -c "cd Syn_SubModule/$m; make flow; cd ../SMC_Top; make flow; cd ../../; touch ${m}_done.tmp; exec csh"
|
||||
else
|
||||
gnome-terminal --geometry=100x30+100*$i+0 --window --title="$m" -x csh -c "cd Syn_SubModule/$m; make flow; cd ../../; touch ${m}_done.tmp; exec csh"
|
||||
fi
|
||||
fi
|
||||
i=$(($i+1))
|
||||
done
|
||||
|
||||
j=1
|
||||
while [ $j == 1 ]
|
||||
do
|
||||
echo "sleep 1"
|
||||
sleep 1
|
||||
i=0
|
||||
k=0
|
||||
for m in ${MODULES[@]}
|
||||
do
|
||||
if [ ${MASK[$i]} == 1 ]; then
|
||||
if [ -f ${m}_done.tmp ]; then
|
||||
echo $i $m "continue"
|
||||
i=$(($i+1))
|
||||
continue
|
||||
else
|
||||
echo $i $m "break"
|
||||
k=1
|
||||
break
|
||||
fi
|
||||
fi
|
||||
i=$(($i+1))
|
||||
done
|
||||
if [ $k == 0 ]; then
|
||||
j=0
|
||||
fi
|
||||
done
|
||||
|
||||
gnome-terminal --geometry=100x30+100*$i+0 --window --title="M8024V_SuperNode" -x csh -c "cd Syn_SubModule/M8024V_SuperNode; make flow; cd ../../; touch M8024V_SuperNode_done.tmp; exec csh"
|
||||
|
||||
j=1
|
||||
while [ $j == 1 ]
|
||||
do
|
||||
echo "sleep 1"
|
||||
sleep 1
|
||||
k=0
|
||||
if [ ! -f M8024V_SuperNode_done.tmp ]; then
|
||||
echo "M8024V_SuperNode break"
|
||||
k=1
|
||||
else
|
||||
echo "M8024V_SuperNode continue"
|
||||
fi
|
||||
if [ $k == 0 ]; then
|
||||
j=0
|
||||
fi
|
||||
done
|
||||
|
||||
date=`date +%Y_%m%d_%H%M`
|
||||
echo $date
|
||||
reportfile=flow_${date}.report
|
||||
touch reportfile
|
||||
i=0
|
||||
for m in ${MODULES[@]}
|
||||
do
|
||||
if [ ${MASK[$i]} == 1 ]; then
|
||||
echo $m >> $reportfile
|
||||
cat Syn_SubModule/${m}/R0_check.result >> $reportfile
|
||||
echo " " >> $reportfile
|
||||
echo " " >> $reportfile
|
||||
fi
|
||||
i=$(($i+1))
|
||||
done
|
||||
|
||||
echo "M8024V_SuperNode:" >> $reportfile
|
||||
cat Syn_SubModule/M8024V_SuperNode/R0_check.result >> $reportfile
|
||||
echo " " >> $reportfile
|
||||
echo " " >> $reportfile
|
||||
|
||||
gnome-terminal --geometry=100x30+110*$i+0 --window --title="M8024V_FullChip" -x csh -c "cd Syn_Top; make flow; cd ..; touch M8024V_FullChip_done.tmp; exec csh"
|
||||
|
||||
j=1
|
||||
while [ $j == 1 ]
|
||||
do
|
||||
echo "sleep 1"
|
||||
sleep 1
|
||||
k=0
|
||||
if [ ! -f M8024V_FullChip_done.tmp ]; then
|
||||
echo "M8024V_FullChip break"
|
||||
k=1
|
||||
else
|
||||
echo "M8024V_FullChip continue"
|
||||
fi
|
||||
if [ $k == 0 ]; then
|
||||
j=0
|
||||
fi
|
||||
done
|
||||
|
||||
echo "M8024V_FullChip:" >> $reportfile
|
||||
cat Syn_Top/R0_check.result >> $reportfile
|
||||
|
||||
rm *_done.tmp
|
||||
@ -1,10 +0,0 @@
|
||||
#!/bin/sh
|
||||
ls | tee te.log
|
||||
rm -f space_occupylist.log
|
||||
touch space_occupylist.log
|
||||
while read LINE
|
||||
do
|
||||
du -hs $LINE | tee -a space_occupylist.log
|
||||
done < te.log
|
||||
rm -f te.log
|
||||
gedit space_occupylist.log
|
||||
@ -1,15 +0,0 @@
|
||||
|
||||
dir=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl`
|
||||
moduleName=`tclsh setModuleName.tcl`
|
||||
|
||||
if [ ! -d ${dir}/src/${moduleName} ]; then
|
||||
echo "Source code is not exist or the dir name is not moduleName. exit."
|
||||
exit
|
||||
fi
|
||||
|
||||
if [ ! -e ${dir}/src/${moduleName}/${moduleName}_filelist.v ]; then
|
||||
echo "Filelist is not exist or the name is not moduleName_filelist. exit."
|
||||
exit
|
||||
fi
|
||||
|
||||
echo "Source codes and filelist is existing."
|
||||
@ -1,3 +0,0 @@
|
||||
#!/bin/bash
|
||||
PROJECTPATH=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl`
|
||||
find $PROJECTPATH -name "*.v" | xargs grep -nP '[\p{Han}]'
|
||||
@ -1,3 +0,0 @@
|
||||
#!/bin/bash
|
||||
PROJECTPATH=`tclsh $RELATIVEPATH/ProjectPathSetting.tcl`
|
||||
find $PROJECTPATH -name "*.v" | xargs grep -n 'timescale'
|
||||
@ -1,18 +0,0 @@
|
||||
#! /usr/bin/perl
|
||||
$i=0;
|
||||
$flag=0;
|
||||
open(NEW,"> $ARGV[1]")||die "ERROR:can't create fzg_result\n";
|
||||
open(OLD,"$ARGV[0]")||die "ERROR:can't open clock_cross.v\n";
|
||||
while(<OLD>){
|
||||
chomp;
|
||||
if(/From Clock Crossing Clocks/) {$flag=1;next;}
|
||||
if(/Information\: Checking \'no\_clock\'/) {$flag=0;}
|
||||
if($flag==1) {
|
||||
@array=split(/\s+/,$_);
|
||||
print NEW "$array[0]\n";
|
||||
for($i=1;$i<@array;$i++)
|
||||
{print NEW "-----> $array[$i]\n";}
|
||||
print NEW "\n\n";}
|
||||
|
||||
|
||||
}
|
||||
@ -1,32 +0,0 @@
|
||||
moduleName=`tclsh setModuleName.tcl`
|
||||
echo $moduleName
|
||||
|
||||
PP=`setPP.sh`
|
||||
echo "PP = ${PP}"
|
||||
PP_date=${PP#*dc.work/}
|
||||
echo "PP_date = ${PP#*dc.work/}"
|
||||
|
||||
cp $RELATIVEPATH/SDC/${moduleName}.sdc NetlistSubmit/${PP_date}/
|
||||
cp $RELATIVEPATH/SDC/${moduleName}_CDC_check.tcl NetlistSubmit/${PP}/
|
||||
sed -i 's/set BACKEND false/set BACKEND true/' NetlistSubmit/${PP_date}/${moduleName}.sdc
|
||||
sed -i 's/set EXTRACT_MODEL true/set EXTRACT_MODEL false/' NetlistSubmit/${PP_date}/${moduleName}.sdc
|
||||
|
||||
if [ ${moduleName} == "SRIO_top" ]; then
|
||||
cp $RELATIVEPATH/SDC/dwc_e25mp_phy_x4_ns_phy_con.tcl NetlistSubmit/${PP}/
|
||||
#sed -i 's/set FLOW SYN/set FLOW STA/' NetlistSubmit/${PP}/const.srio3_ep_phy_top.tcl
|
||||
fi
|
||||
|
||||
if [ ${moduleName} == "fullchip_top" ]; then
|
||||
cp ${PP}/result/*.sv NetlistSubmit/${PP} -rf
|
||||
sed -i 's/set PR true/set PR false/' NetlistSubmit/${PP}/${moduleName}.sdc
|
||||
cp $RELATIVEPATH/SDC/M66AK_FullChip_skew_check.tcl NetlistSubmit/${PP}/
|
||||
cp $RELATIVEPATH/SDC/MaxMinDelay.tcl NetlistSubmit/${PP}/
|
||||
#remove power and ground pins.
|
||||
#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip_CLC_Top.sv
|
||||
#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip_CrossNet.sv
|
||||
#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip_excluding_CLC_RESETC_CrossNet.sv
|
||||
#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip_RESETC.sv
|
||||
#$RELATIVEPATH/Scripts/emptyPortValue.pl NetlistSubmit/${PP}/M66AK_FullChip.sv
|
||||
fi
|
||||
|
||||
|
||||
@ -1,200 +0,0 @@
|
||||
#!/usr/bin/python
|
||||
#company: nudt-wdzs-671
|
||||
#filename: creat_dummy.py
|
||||
#description: generate the dummy file of a verilog top file
|
||||
#author: liusheng
|
||||
#revision List:
|
||||
#(rn: date : modifier: description)
|
||||
#r1: 2019.01.12 the first copy
|
||||
#r2: 2020.04.05 solve the problem that the signalname inlcudes "input" / "output" or "inout", such as "input bscan_select_jtag_input; "
|
||||
#r3: 2020.05.05 solve the problem that the file inlcudes "`resetall or `timescale".
|
||||
#r4: 2020.05.11 fix the bug in "\n"
|
||||
|
||||
import sys
|
||||
import re
|
||||
|
||||
####main###########################################################################################
|
||||
print "welcome to use".center(100,"-")
|
||||
print 'This tool can generate the dummy file of a verilog file.'
|
||||
print 'please type "creat_dummy.py src.v dst.v" it will geneate the dummy file (dst.v) of src.v.'
|
||||
print 'The author of this sofware is liusheng from national university of defense technology, China.'
|
||||
print "welcome to use".center(100,"-")
|
||||
print ""
|
||||
|
||||
filepath=sys.argv[1]
|
||||
file_in=open(filepath,"r")
|
||||
file_all_1=file_in.read()
|
||||
|
||||
modulename=sys.argv[2];
|
||||
|
||||
realmodulename=modulename.strip('\.v');
|
||||
|
||||
#delete all the commenting
|
||||
file_all_2=re.sub('\/\/.*?\n','\n',file_all_1)
|
||||
file_all_3=re.sub('\/\*.*?\*\/','',file_all_2)
|
||||
file_all_4=re.sub('\/\*[\s\S]*?\*\/','\n',file_all_3)
|
||||
#delete all the `, such as "`resetall or `timescale".
|
||||
file_all_4=re.sub('`.*?\n','\n',file_all_4)
|
||||
|
||||
#print file_all_4
|
||||
|
||||
#delete declare
|
||||
file_all_5=re.sub('.*module[\s\S]*?;','',file_all_4)
|
||||
|
||||
#print file_all_5
|
||||
|
||||
#get declare
|
||||
all_declare_1=re.findall('.*module[\s\S]*?\)',file_all_4)
|
||||
all_declare=re.sub(',|\)',';',''.join(all_declare_1))
|
||||
|
||||
#print all_declare
|
||||
|
||||
#fix \n
|
||||
file_all_1=all_declare+file_all_5
|
||||
#file_all_2=file_all_1.replace("\n","")
|
||||
file_all_3=file_all_1.replace(";",";\n")
|
||||
|
||||
#fix reg wire
|
||||
file_all_4=file_all_3.replace("reg","")
|
||||
file_all=file_all_4.replace("wire","")
|
||||
|
||||
|
||||
|
||||
#replace the true "parameter localparam input output inout" as "PARAMETER LOCALPARAM INPUT OUTPUT INOUT"
|
||||
|
||||
file_all=re.sub(r'^parameter','PARAMETER',file_all);
|
||||
file_all=re.sub(r'\sparameter','\nPARAMETER',file_all);
|
||||
file_all=re.sub(r' parameter',' PARAMETER',file_all);
|
||||
file_all=re.sub(r'^localparam','LOCALPARAM',file_all);
|
||||
file_all=re.sub(r'\slocalparam','\nLOCALPARAM',file_all);
|
||||
file_all=re.sub(r' localparam',' LOCALPARAM',file_all);
|
||||
file_all=re.sub(r'^input','INPUT',file_all);
|
||||
file_all=re.sub(r'\sinput','\nINPUT',file_all);
|
||||
file_all=re.sub(r' input',' INPUT',file_all);
|
||||
file_all=re.sub(r'\soutput','\nOUTPUT',file_all);
|
||||
file_all=re.sub(r' output',' OUTPUT',file_all);
|
||||
file_all=re.sub(r'^output','OUTPUT',file_all);
|
||||
file_all=re.sub(r'\sinout','\nINOUT',file_all);
|
||||
file_all=re.sub(r' inout',' INOUT',file_all);
|
||||
file_all=re.sub(r'^inout','INOUT',file_all);
|
||||
|
||||
#print file_all
|
||||
|
||||
|
||||
#find all parameter
|
||||
allparameter=re.findall('.*PARAMETER(.*?);',file_all)
|
||||
|
||||
#find all localparam
|
||||
alllocalparam=re.findall('.*LOCALPARAM(.*?);',file_all)
|
||||
|
||||
#find all input
|
||||
allinput_ini=re.findall('.*INPUT(.*?);',file_all)
|
||||
|
||||
allinput=",".join(allinput_ini)
|
||||
|
||||
#find all true input
|
||||
alltrueinput=re.sub('\[.*?\]|\s','',allinput)
|
||||
|
||||
#find all output
|
||||
alloutput_ini=re.findall('.*OUTPUT(.*?);',file_all)
|
||||
alloutput=",".join(alloutput_ini)
|
||||
|
||||
#find all true output
|
||||
alltrueoutput=re.sub('\[.*?\]|\s','',alloutput)
|
||||
|
||||
#find all inout
|
||||
allinout_ini=re.findall('.*inout(.*?);',file_all)
|
||||
allinout=",".join(allinout_ini)
|
||||
|
||||
#find all true input
|
||||
alltrueinout=re.sub('\[.*?\]|\s','',allinout)
|
||||
|
||||
file_out=open(modulename,"w")
|
||||
|
||||
#print allparameter
|
||||
i=0
|
||||
j=0
|
||||
|
||||
print>>file_out,"module "+realmodulename+"("
|
||||
print>>file_out,"//output"
|
||||
for p in list(re.split(",",alltrueoutput)):
|
||||
i=i+len(p)+2
|
||||
if(i>70):
|
||||
print>>file_out,'\n'+p+',',
|
||||
i=len(p)+2
|
||||
else:
|
||||
print>>file_out,p+',',
|
||||
|
||||
i=0
|
||||
if(alltrueinout!=''):
|
||||
print>>file_out,"\n//inout"
|
||||
for p in list(re.split(",",alltrueinout)):
|
||||
i=i+len(p)+2
|
||||
if(i>70):
|
||||
print>>file_out,'\n'+p+',',
|
||||
i=len(p)+2
|
||||
else:
|
||||
print>>file_out,p+',',
|
||||
|
||||
print>>file_out,""
|
||||
print>>file_out,"//input"
|
||||
i=0
|
||||
for p in list(re.split(",",alltrueinput)):
|
||||
j=j+1
|
||||
i=i+len(p)+2
|
||||
if(i>70):
|
||||
if(len(re.split(",",alltrueinput))==j):
|
||||
print>>file_out,'\n'+p
|
||||
else:
|
||||
print>>file_out,'\n'+p+',',
|
||||
i=len(p)+2
|
||||
else:
|
||||
if(len(re.split(",",alltrueinput))==j):
|
||||
print>>file_out,p
|
||||
else:
|
||||
print>>file_out,p+',',
|
||||
print>>file_out,");"
|
||||
print>>file_out,""
|
||||
|
||||
for p in list(allparameter):
|
||||
p=re.sub('\s','',p)
|
||||
print>>file_out,' parameter '+p+';'
|
||||
|
||||
for p in list(alllocalparam):
|
||||
p=re.sub('\s','',p)
|
||||
print>>file_out,' localparam '+p+';'
|
||||
|
||||
|
||||
print>>file_out,""
|
||||
for p in list(allinput_ini):
|
||||
p=re.sub('\s','',p)
|
||||
print>>file_out," input "+p+";"
|
||||
|
||||
print>>file_out,""
|
||||
for p in list(allinout_ini):
|
||||
p=re.sub('\s','',p)
|
||||
print>>file_out," inout "+p+";"
|
||||
|
||||
print>>file_out,""
|
||||
for p in list(alloutput_ini):
|
||||
p=re.sub('\s','',p)
|
||||
print>>file_out," output "+p+";"
|
||||
|
||||
print>>file_out,""
|
||||
for p in list(re.split(",",alltrueoutput)):
|
||||
if("rst" in p)|("reset" in p)|("RST" in p)|("RESET" in p):
|
||||
print>>file_out," assign "+p+"=1'b1;"
|
||||
elif ("JTAGC_TDO" in p):
|
||||
print>>file_out," assign "+p+"=JTAGC_TDI;"
|
||||
else:
|
||||
print>>file_out," assign "+p+"='b0;"
|
||||
|
||||
|
||||
print>>file_out,""
|
||||
for p in list(re.split(",",alltrueinout)):
|
||||
if(p!=""):
|
||||
print>>file_out," assign "+p+"='b0;"
|
||||
|
||||
print>>file_out,"endmodule"
|
||||
|
||||
####main###########################################################################################
|
||||
@ -1,9 +0,0 @@
|
||||
This step recommends goals to be used during the entire
|
||||
RTL development cycle for new RTL blocks.
|
||||
|
||||
When RTL is almost ready and final handoff checks are being performed.
|
||||
At this time, majority of GuideWare New_RTL goals should be run after
|
||||
every ECO.
|
||||
|
||||
This step also includes a set of Optional goals at each stage.
|
||||
Design teams should inspect these goals for applicability to their design.
|
||||
@ -1,3 +0,0 @@
|
||||
The aim of this goal is to check the simulation readiness of the design. At this stage the designer is typically interested in the following
|
||||
* The designs meets basic connectivity checks such as floating inputs, width mismatch
|
||||
* The design meets basic simulation prerequisites that can cause functional errors or possible race conditions
|
||||
@ -1,34 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : adv_lint_setup
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
adv_lint_setup mixed
|
||||
*
|
||||
Defines Clocks and Resets
|
||||
*
|
||||
This step is used to find the clocks and resets in a design. Follow steps below
|
||||
to complete initial clocks and resets constraints creation:
|
||||
1- Understand your design clocks architecture by exploring clocks and resets
|
||||
as identified by rules run in this template. Black box clocks need to be
|
||||
resolved.
|
||||
2- Copy autoclocks.sgdc and autoresets.sgdc into a new constraint file and
|
||||
edit the clocks to provide valid clock/reset sources and remove all
|
||||
non clocks/resets signals from the file
|
||||
In addition you can also add known case-analysis under which you want to do the
|
||||
analysis
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
-mixed
|
||||
-policy=clock-reset
|
||||
-rules Clock_info01
|
||||
-rules Reset_info01
|
||||
-rules Info_Case_Analysis
|
||||
@ -1,65 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="05/10/10 16:52:30" />
|
||||
<title>adv_lint_setup</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131676"> </a><h2 class="pHeading1">
|
||||
adv_lint_setup
|
||||
</h2>
|
||||
<a name="wp1131677"> </a><p class="pBody">
|
||||
The aim of this goal is to help the user in finding the clocks and resets. Review clocks and resets reported by Clock_info01 and Reset_info01. For viewing constant propagation in the design, the user can look at Info_Case_Analysis.
|
||||
</p>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,43 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : adv_lint_struct
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
// 1.1.0 16-Apr-2014 Av_fsm01 deleted
|
||||
//
|
||||
// Copyright Atrenta Inc, 2013. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
adv_lint_verify_struct mixed
|
||||
*
|
||||
Helps identify and fix structural problems and explore assertion checking opportunities
|
||||
in a design without performing the actual checks.
|
||||
Reports design complexity characteristics.
|
||||
*
|
||||
The adv_lint_verify_struct goal analyzes structural problems and assertion checking
|
||||
opportunities in the design.
|
||||
=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
-mixed
|
||||
-policies=auto-verify
|
||||
|
||||
-rule=Av_Info_Case_Analysis // Highlights case-analysis settings
|
||||
-rule=Av_fsminf01 // Reports all the FSMs in the design
|
||||
-rule=Av_fsminf02 // Reports all the interacting FSMs in the design
|
||||
-rule=Av_fsm_analysis // Reports all Fsm related issues like deadlock, livelock, unreachable state and dead transitions
|
||||
-rules=Av_divide_by_zero // Report Divide/Modulus by zero issue
|
||||
-rule=Av_case01 // Reports all the sensitive case items which are not specified
|
||||
-rule=Av_case02 // Reports the case statements with parallel case pragma which have overlapping case items
|
||||
-rule=Av_deadcode01 // Reports redundant logic in the design
|
||||
-rule=Av_bus01 // Reports all the bus contentions in the design
|
||||
-rule=Av_bus02 // Reports all the floating busses in the design
|
||||
-rule=Av_dontcare01 // Reports sensitizable X-assignments in the design
|
||||
-rule=Av_range01 // Reports array bound violation
|
||||
-rule=Av_complexity01 // Reports design characteristics and complexity for all the RTL modules and FSMs in the design
|
||||
|
||||
-audit=yes
|
||||
+syntharg -ignoreHangingFF
|
||||
@ -1,72 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="06/10/10 14:48:47" />
|
||||
<title>adv_lint_verify_struct</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131532"> </a><h2 class="pHeading1">
|
||||
adv_lint_verify_struct
|
||||
</h2>
|
||||
<a name="wp1131567"> </a><p class="pBody">
|
||||
The aim of this goal is to identify and fix structural problems, report design complexity, and explore assertion checking opportunities in a design
|
||||
The violations can be debugged and fixed in the following order
|
||||
</p>
|
||||
<div class="pSmartList1"><ol type="1" class="pSmartList1">
|
||||
<a name="wp1131568"> </a><div class="pSmartList1"><li>Analyze reported FSMs</li></div>
|
||||
<a name="wp1131740"> </a><div class="pSmartList1"><li>Analyze reported design complexity</li></div>
|
||||
<a name="wp1131741"> </a><div class="pSmartList1"><li>Analyze assertion opportunities for functional rules</li></div>
|
||||
</p>
|
||||
</ol></div>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,41 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : adv_lint_verify
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
// 1.1.0 16-Apr-2014 Av_fsm01 deleted
|
||||
//
|
||||
// Copyright Atrenta Inc, 2013. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
adv_lint_verify mixed
|
||||
*
|
||||
Helps identify and fix functional problems related to FSMs, case statements, dead and static code,
|
||||
busses, and x assignment.
|
||||
Reports design complexity characteristics.
|
||||
*
|
||||
The adv_lint_verify goal analyzes functional problems in the design.
|
||||
=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
-mixed
|
||||
-policies=auto-verify
|
||||
|
||||
-rule=Av_Info_Case_Analysis // Highlights case-analysis settings
|
||||
-rule=Av_fsminf01 // Reports all the FSMs in the design
|
||||
-rule=Av_fsminf02 // Reports all the interacting FSMs in the design
|
||||
-rule=Av_fsm_analysis // Reports all Fsm related issues like deadlock, livelock, unreachable state and dead transitions
|
||||
-rule=Av_divide_by_zero // Report Divide/Modulus by zero issue
|
||||
-rule=Av_case01 // Reports all the sensitive case items which are not specified
|
||||
-rule=Av_case02 // Reports the case statements with parallel case pragma which have overlapping case items
|
||||
-rule=Av_deadcode01 // Reports redundant logic in the design
|
||||
-rule=Av_bus01 // Reports all the bus contentions in the design
|
||||
-rule=Av_bus02 // Reports all the floating busses in the design
|
||||
-rule=Av_dontcare01 // Reports sensitizable X-assignments in the design
|
||||
-rule=Av_range01 // Reports array bound violation
|
||||
-rule=Av_complexity01 // Reports design characteristics and complexity for all the RTL modules and FSMs in the design
|
||||
|
||||
+syntharg -ignoreHangingFF
|
||||
@ -1,72 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="06/10/10 14:48:47" />
|
||||
<title>adv_lint_verify</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131532"> </a><h2 class="pHeading1">
|
||||
adv_lint_verify
|
||||
</h2>
|
||||
<a name="wp1131567"> </a><p class="pBody">
|
||||
The aim of this goal is to analyze all the functional problems in the design. This runs all the functional rules of the Advanced Lint policy.
|
||||
The violations can be debugged and fixed in the following order
|
||||
</p>
|
||||
<div class="pSmartList1"><ol type="1" class="pSmartList1">
|
||||
<a name="wp1131568"> </a><div class="pSmartList1"><li>Analyze and resolve x-assignments, divide/modulus by zero issues, generation and propagation problems in the design reported by the rules Av_dontcare01, Av_divide_by_zero, Av_bus01, Av_bus02 and Av_range01.</li></div>
|
||||
<a name="wp1131740"> </a><div class="pSmartList1"><li>Fix the FSM-related issues and case statement related issues reported by the rules Av_fsm_analysis, Av_case01 and Av_case02</li></div>
|
||||
<a name="wp1131741"> </a><div class="pSmartList1"><li>Fix the redundant code related violations reported by Av_deadcode01 and Av_staticnet01 rules.</li></div>
|
||||
</p>
|
||||
</ol></div>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,81 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass Methodology2.0 Goal File
|
||||
//
|
||||
// Goal Name : lint_functional_rtl
|
||||
// Version: 5.6.1
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 26-Nov-2014 Initial version
|
||||
// 5.4.1 04-Mar-2015 Made following changes
|
||||
// Removed arg: +syntharg -ignoreHanginFF
|
||||
// Added use_inferred_clocks & use_inferred_resets
|
||||
//
|
||||
// 5.5.0 16-Apr-2015 Added Av_signed_unsigned_mismatch and Av_width_mismatch_expr
|
||||
//
|
||||
// 5.6.0 18-Nov-2015 5.6 Added Following Rules
|
||||
// Rule Name Policy GW Type
|
||||
// ===============================================
|
||||
// Av_width_mismatch_expr02 auto-verify MUST
|
||||
// Av_width_mismatch_expr03 auto-verify MUST
|
||||
// Av_dontcare_mismatch auto-verify MUST
|
||||
// Av_case_default_missing auto-verify MUST
|
||||
// Av_case_default_redundant auto-verify MUST
|
||||
//
|
||||
// 5.6.1 29-Mar-2015 Removed use_inferred_resets & use_inferred_clocks
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
lint_functional_rtl mixed
|
||||
*
|
||||
Helps identify width related issues in assignment, case expression-select, instance
|
||||
port connection and function arguments using functional analysis
|
||||
*
|
||||
This goal uses functional analysis to identify width related issues in the design.
|
||||
=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
-policies=auto-verify
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
-nocheckoverflow='yes' // Width will be calculated as per LRM rather best fit.
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
-rule=Av_Info_Case_Analysis // Highlights case-analysis settings
|
||||
|
||||
-rule=Av_width_mismatch_assign // LHS width is less than RHS width of assignment (Truncation)
|
||||
|
||||
-rule=Av_width_mismatch_case // Case expression width does not match case select expression width
|
||||
|
||||
-rule=Av_width_mismatch_port // Instance port connection has different width compared to the port definition
|
||||
|
||||
-rule=Av_width_mismatch_function // Bit-width of function call arguments must match bit-width of the corresponding function definition arguments
|
||||
|
||||
// Do not mix signed & unsigned variables/constants in expressions, assignment statements or in comparisons
|
||||
-rule=Av_signed_unsigned_mismatch
|
||||
|
||||
//Bit-width of operands of a logical operator must match
|
||||
-rule=Av_width_mismatch_expr
|
||||
|
||||
-rule=Av_case_default_missing // A case statement(or selected signal assignment) does not have a default clause
|
||||
|
||||
-rule=Av_width_mismatch_expr03 // Unequal length in arithmetic comparison operator
|
||||
|
||||
-rule=Av_width_mismatch_expr02 // Unequal length operands in bit wise logical/arithmetic/relational operator
|
||||
|
||||
-rule=Av_dontcare_mismatch // Use of don't-care except in case labels may lead to simulation/synthesis mismatch
|
||||
|
||||
-rules Av_case_default_redundant // A case statement marked full_case or a priority/unique case statement have a default clause.
|
||||
|
||||
@ -1,72 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="06/10/10 14:48:47" />
|
||||
<title>adv_lint_verify</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131532"> </a><h2 class="pHeading1">
|
||||
adv_lint_verify
|
||||
</h2>
|
||||
<a name="wp1131567"> </a><p class="pBody">
|
||||
The aim of this goal is to analyze width related problems in the design. This runs all the functional rules of the Advanced Lint policy.
|
||||
The violations can be debugged and fixed in the following order
|
||||
</p>
|
||||
<div class="pSmartList1"><ol type="1" class="pSmartList1">
|
||||
<a name="wp1131568"> </a><div class="pSmartList1"><li>Analyze and resolve assignment width mismatch in the design reported by the rules Av_width_mismatch_assign.</li></div>
|
||||
<a name="wp1131740"> </a><div class="pSmartList1"><li>Analyze and resolve case expression width mismatch in the design reported by the rules Av_width_mismatch_case</li></div>
|
||||
<a name="wp1131741"> </a><div class="pSmartList1"><li>Fix the width mismatch in arguments of functional calls and port connection in instantiation reported by Av_width_mismatch_port and Av_width_mismatch_function rules.</li></div>
|
||||
</p>
|
||||
</ol></div>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,3 +0,0 @@
|
||||
The aim of this goal is to check the simulation readiness of the design. At this stage the designer is typically interested in the following
|
||||
* The designs meets basic connectivity checks such as floating inputs, width mismatch
|
||||
* The design meets basic simulation prerequisites that can cause functional errors or possible race conditions
|
||||
@ -1,93 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : cdc_abstract
|
||||
// Version: 1.7.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date SG Ver Comments
|
||||
// 1.0.0 18-Feb-2013 5.0 Initial version
|
||||
// 1.1.0 26-Apr-2013 5.1 Parameter enable_handshake removed
|
||||
// 1.4.0 12-Feb-2014 5.2.1 Clock_info18, enable_fifo=strict removed
|
||||
// Setup_port01, Setup_blackbox01 added
|
||||
// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency
|
||||
// 1.10.2 23-Feb-2015 5.4.1 Parameter decompile_block_constraints added
|
||||
// Parameter sdc_generate_cfp added
|
||||
// Rule FalsePathSetup added
|
||||
// 1.13.0 03-Feb-2017 2017.03 Parameter reset_reduce_pessimism added
|
||||
// 1.14.0 26-Apr-2017 2017.03-SP1 Parameters check_multiclock_bbox, cdc_qualifier_depth, clock_reduce_pessimism, reset_reduce_pessimism, cdc_reduce_pessimism, include_block_interface, use_block_interface added
|
||||
|
||||
// 1.15.0 18-July-2017 2017.12 Parameter use_inferred_abstract_port added
|
||||
// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
cdc_abstract mixed
|
||||
*
|
||||
Abstraction of a block for CDC verification at a higher level of hierarchy
|
||||
*
|
||||
This step is used to abstract a block which is to be used at higher level of
|
||||
hierarchy for CDC verification. The abstracted model helps in following:
|
||||
- Less run-time at top-level
|
||||
- Less noise at top-level as no violations will be reported inside the blocks
|
||||
|
||||
Perform this step after doing CDC verification of block.
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=clock-reset
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
-mixed //allow mixed language
|
||||
-enable_const_prop_thru_seq //allow to propagate beyond the sequential elements
|
||||
-use_advcdc_features //Run Advanced CDC Rules in restore mode
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
-enable_mux_sync=all //MUX Synchronization schemes
|
||||
-enable_and_sync=yes //Enables the AND Gate Synchronization Scheme
|
||||
-distributed_fifo=yes //Enables detection of FIFOs based on distributed memories
|
||||
-fa_disable_sync_fifo=yes //Specifies whether functional analysis should be performed on synchronous FIFO structures
|
||||
-strict_sync_check=yes //Allows combinational logic between the source and destination flip-flops
|
||||
-enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic
|
||||
-hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution
|
||||
-block_abstract //Generates relevant CDC constraints for block abstraction
|
||||
-sdc_generate_cfp=yes //Inferring cdc_false_path for asynchronous clocks in different domains
|
||||
-decompile_block_constraints // Create merged abstract model
|
||||
-reset_reduce_pessimism=same_data_reset_flop,remove_overlap //Remove overlap between reset sync check and async reset (reset_sync02) rules
|
||||
|
||||
-include_block_interface=abstract //Put SV interface information into the abstract model
|
||||
-use_block_interface //Use the SV internface information in the abstract model
|
||||
-check_multiclock_bbox=yes //Clock domain crossing involving the unconstrained pins of black-box instances on destination side and receiving multiple clock are ignored
|
||||
-cdc_qualifier_depth=3 //Default is infinite. This leads to some wrong qualifiers
|
||||
-clock_reduce_pessimism=latch_en,mux_sel_derived,check_enable_for_glitch,ignore_same_domain
|
||||
-cdc_reduce_pessimism=mbit_macro,no_convergence_at_syncreset,no_convergence_at_enable,use_multi_arc,clock_crossing,no_unate_reconv,clock_on_ports,ignore_multi_domain //Let multi-domain source synchronizers will be recognized in Ac_sync but Ac_glitch03 will continue to report the issue.
|
||||
-use_inferred_abstract_port=yes
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Setup_port01 //Reports unconstrained ports summary for top design unit
|
||||
|
||||
-rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes
|
||||
|
||||
-rules Ac_abstract01 //Generates relevant SpyGlass CDC constraints for block abstraction
|
||||
|
||||
-rules Info_Case_Analysis // Constant propagation in schematic display
|
||||
|
||||
-rules FalsePathSetup //Cases where cdc_false_path constraint is not used by any crossing in the design
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,67 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="06/10/10 14:48:47" />
|
||||
<title>cdc_abstract</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131532"> </a><h2 class="pHeading1">
|
||||
cdc_abstract
|
||||
</h2>
|
||||
<a name="wp1131567"> </a><p class="pBody">
|
||||
The aim of this goal is to generate abstract model of a block. This goal reports an informational message by rule Ac_abstract01, which points to the SGDC file containing abstract model.
|
||||
|
||||
|
||||
</p>
|
||||
<a name="wp1131568"> </a><div class="pSmartList1"><li>Use generated abstract models of blocks at SoC level for CDC verification and abstraction validation checks. You can provide the generated abstract model just with the RTL interface of blocks, without full definitions of blocks.</li></div>
|
||||
</p>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,69 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : cdc_setup
|
||||
// Version: 1.7.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date SG Ver Comments
|
||||
// 1.0.0 18-Feb-2013 5.0 Initial version
|
||||
// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency
|
||||
// 1.12.0 18-Nov-2015 5.6.0 Parameter handle_combo_arc=yes added
|
||||
// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
cdc_setup mixed
|
||||
*
|
||||
Define Clocks and Resets
|
||||
*
|
||||
This step is used to find the clocks and resets in a design. Follow steps below
|
||||
to complete initial clocks and resets constraints creation:
|
||||
1- Understand your design clocks architecture by exploring clocks and resets
|
||||
as identified by rules run in this template. Black box clocks need to be
|
||||
resolved by assuming path through black boxes (use assume_path constraint)
|
||||
2- Copy autoclocks.sgdc and autoresets.sgdc into a new constraint file and
|
||||
edit the clocks to provide valid clock/reset sources and remove all
|
||||
non clocks/resets signals from the file
|
||||
In addition you can also add known case-analysis under which you want to do CDC analysis.
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=clock-reset
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
-mixed //allow mixed language
|
||||
-enable_const_prop_thru_seq //allow to propagate beyond the sequential elements
|
||||
-use_advcdc_features //Run Advanced CDC Rules in restore mode
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
-enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic
|
||||
-hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution
|
||||
-handle_combo_arc=yes //propagate clocks through lib cells
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Setup_clock01 // Generates information needed for Clock Setup
|
||||
|
||||
-rules Clock_info01 // Clock candidates in the design
|
||||
|
||||
-rules Reset_info01 // Asynchronous and synchronous preset and clear candidates in the design
|
||||
|
||||
-rules Info_Case_Analysis // Constant propagation in schematic display
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,137 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : cdc_setup_check
|
||||
// Version: 1.12.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date SG Ver Comments
|
||||
// 1.0.0 18-Feb-2013 5.0 Initial version
|
||||
// 1.1.0 05-Oct-2013 5.2 Rule Clock_check10 added
|
||||
// 1.4.0 12-Feb-2014 5.2.1 Clock_info18 removed
|
||||
// Ar_converge01, Setup_req01, Setup_port01, Setup_blackbox01 added
|
||||
// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency
|
||||
// 1.10.0 17-Dec-2014 5.4.1 Setup_req01 removed
|
||||
// 1.10.2 23-Feb-2015 5.4.1 Rule FalsePathSetup added
|
||||
// Rule Setup_library01 added
|
||||
// Parameter sdc_generate_cfp added
|
||||
// Rule Ac_clockperiod01 removed
|
||||
// Rule Ac_clockperiod02 removed
|
||||
// 1.12.0 16-Nov-2016 2016.06-SP2 Rules Clock_info02 and Reset_info02 removed
|
||||
// 1.13.0 03-Feb-2017 2017.03 Added parameter report_common_reset
|
||||
// 1.14.0 26-Apr-2017 2017.03-SP1 Rules Clock_info05c, Clock_info01, Reset_info01 added
|
||||
// Rule Reset_check10 removed
|
||||
// 1.15.0 18-July-2017 2017.12 Parameter use_inferred_abstract_port added
|
||||
// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added
|
||||
// 1.18.0 04-Dec-2018 2018.09 QualifierSetup rule removed due to unneccessary noise STAR #9001291972
|
||||
//
|
||||
// Copyright Atrenta Inc, 2016. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
cdc_setup_check mixed
|
||||
*
|
||||
Clocks and Resets Setup Checks
|
||||
*
|
||||
This step is used to check setup correctness and completeness; it is very
|
||||
important to fix all violations reported in this step to avoid false violations
|
||||
due to incorrect/incomplete setup . Some examples,
|
||||
1- Ensure all flops are receiving a clock
|
||||
2- Ensure case analysis is defined preventing multiple clocks controlling
|
||||
the same flop
|
||||
3- Ensure multiple clocks are not defined on the same clock path
|
||||
4- Periods, edge-list and domains are defined properly for clocks
|
||||
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=clock-reset
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
-mixed //allow mixed language
|
||||
-enable_const_prop_thru_seq //allow to propagate beyond the sequential elements
|
||||
-use_advcdc_features //Run Advanced CDC Rules in restore mode
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
-enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic
|
||||
-hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution
|
||||
-sdc_generate_cfp=yes //Inferring cdc_false_path for asynchronous clocks in different domains
|
||||
-report_common_reset=yes //Reports the common reset source skipping buf/inv and MUX/combo gates acting as buffer
|
||||
-use_inferred_abstract_port=yes
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Clock_info03a // Reports unconstrained clock nets
|
||||
-overloadrules Clock_info03a+severity=Error
|
||||
|
||||
-rules Clock_info05 // MUX descriptions where two or more clock signals converge
|
||||
-overloadrules Clock_info05+severity=Error
|
||||
|
||||
## -rules Clock_info05a // Signals on which the set_case_analysis should be set to control MUXed clock selection
|
||||
-overloadrules Clock_info05a+severity=Error
|
||||
|
||||
-rules Clock_info05b // Combinational gates other than MUXes where two or more clock signals converge
|
||||
-overloadrules Clock_info05b+severity=Error
|
||||
|
||||
-rules Ac_resetvalue01 // Missing -value field of the reset constraint defined in an SGDC file
|
||||
-overloadrules Ac_resetvalue01+severity=Error
|
||||
|
||||
-rules Reset_info09a // Reports Unconstrained asynchronous reset nets
|
||||
-overloadrules Reset_info09a+severity=Error
|
||||
|
||||
-rules Clock_converge01 // Clocks whose multiple fan-outs converge
|
||||
-overloadrules Clock_converge01+severity=Error
|
||||
|
||||
-rules Ar_converge01 //Reports a reset signal whose multiple fan-outs converge
|
||||
|
||||
-rules Reset_check03 //Reset signals that are being used at both levels to set or reset flip-flops synchronously
|
||||
-overloadrules Reset_check03+severity=Error
|
||||
|
||||
-rules Reset_check11 //Asynchronous resets used as both active-high and active-low
|
||||
-overloadrules Reset_check11+severity=Error
|
||||
|
||||
-rules Reset_check12 // Flops that do not get active reset during power on reset
|
||||
-overloadrules Reset_check12+severity=Error
|
||||
|
||||
-rules Clock_info03b //Flip-flops,latches where the data pins are tied to a constant value
|
||||
|
||||
-rules Clock_info03c // Reports Flip-flops or latches where the clock/enable pin is set to a constant
|
||||
-overloadrules Clock_info03c+severity=Error
|
||||
|
||||
-rules Setup_port01 //Reports unconstrained ports summary for top design unit
|
||||
|
||||
-rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes
|
||||
|
||||
-rules Clock_check10 // Reports clocks being used as data
|
||||
|
||||
-rules Clock_info15 // Generates clock domain information for primary ports
|
||||
|
||||
-rules Ar_syncrst_setupcheck01 // Reports constant value on functional flops in synchronous reset deassert-mode
|
||||
|
||||
-rules Info_Case_Analysis // Constant propagation in schematic display
|
||||
|
||||
-rules Clock_info05c //Reports unconstrained MUXes which do not receive clocks in all its data inputs
|
||||
|
||||
-rules FalsePathSetup //Cases where cdc_false_path constraint is not used by any crossing in the design
|
||||
|
||||
-rules Setup_library01 //Reports incomplete definition of library pins for CDC
|
||||
|
||||
-rules Clock_info01 // Clock candidates in the design
|
||||
|
||||
-rules Reset_info01 // Asynchronous and synchronous preset and clear candidates in the design
|
||||
|
||||
-ignorerules QualifierSetup //Removed due to unneccessary noise
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,82 +0,0 @@
|
||||
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|
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|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131462"> </a><h2 class="pHeading1">
|
||||
cdc_setup_check
|
||||
</h2>
|
||||
<a name="wp1131682"> </a><p class="pBody">
|
||||
The aim of this goal is to check setup correctness and completeness. To avoid false analysis due to incorrect/incomplete setup, the user should fix all violations reported during this step. The violations can be debugged and fixed in the following order:
|
||||
</p>
|
||||
<div class="pSmartList1"><ol type="1" class="pSmartList1">
|
||||
<a name="wp1131683"> </a><div class="pSmartList1"><li>Analyze and fix clock setup issues reported by the following rules:</li></div>
|
||||
<a name="wp1131684"> </a><p class="pBodyRelative">
|
||||
Clock_info03a, Clock_info03b, Clock_info03c, Clock_info05, Clock_info05c, Clock_info05b, Clock_info01, Reset_info01, Clock_converge01, Ar_converge01, FalsePathSetup, Setup_library01
|
||||
</p>
|
||||
<a name="wp1131479"> </a><div class="pSmartList1"><li>Analyze and fix reset setup issues reported by the following rules:</li></div>
|
||||
<a name="wp1131480"> </a><p class="pBodyRelative">
|
||||
Reset_info09a, Ac_resetvalue01, Ar_syncrst_setupcheck01
|
||||
</p>
|
||||
<a name="wp1131493"> </a><div class="pSmartList1"><li>Analyze and fix basic issues in reset logic reported by the following rules:</li></div>
|
||||
<a name="wp1131494"> </a><p class="pBodyRelative">
|
||||
Reset_check03, Reset_check11, Reset_check12
|
||||
</p>
|
||||
<a name="wp1131980"> </a><div class="pSmartList1"><li>Review report and SGDC file generated by rules Clock_info15, Setup_port01, Setup_blackbox01 to ensure all IOs are properly constrained</li></div>
|
||||
</p>
|
||||
<a name="wp1131493"> </a><div class="pSmartList1"><li>Review and prune the quasi_static constraints in SGDC file generated by Setup_quasi_static01 rule and provide the SGDC file in CDC verification goals</li></div>
|
||||
</ol></div>
|
||||
|
||||
|
||||
|
||||
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|
||||
|
||||
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|
||||
|
||||
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|
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|
||||
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|
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||||
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|
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|
||||
<blockquote>
|
||||
<a name="wp1131676"> </a><h2 class="pHeading1">
|
||||
cdc_setup
|
||||
</h2>
|
||||
<a name="wp1131677"> </a><p class="pBody">
|
||||
The aim of this goal is to help the user in finding the clocks and resets. Review clocks and resets reported by Clock_info01, and Reset_info01.
|
||||
</p>
|
||||
<a name="wp1131457"> </a><p class="pBody">
|
||||
For an in-depth analysis and understanding of clocks architecture, the user can look at Setup_clock01. For viewing constant propagation in the design, the user can look at Info_Case_Analysis.
|
||||
</p>
|
||||
|
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|
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|
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@ -1,245 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : cdc_verify
|
||||
// Version: 1.14.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date SG Ver Comments
|
||||
// 1.0.0 18-Feb-2013 5.0 Initial version
|
||||
// 1.1.0 26-Apr-2013 5.1 Rule Ar_syncrst_setupcheck01 added
|
||||
// Parameter enable_handshake removed
|
||||
// 1.2.0 06-Aug-2013 5.1.1 Rules Ac_handshake01 and Ac_handshake02 removed
|
||||
// 1.3.0 04-Oct-2013 5.2 Rule Clock_check10 added
|
||||
// Rules Ac_coherency01a, Ac_coherency02a added
|
||||
// 1.4.0 12-Feb-2014 5.2.1 Clock_info18, Ac_fifo01, Ac_cdc08, enable_fifo removed
|
||||
// Ar_converge01, Setup_req01, Ac_conv04, Ac_conv05, Ac_coherency06, Setup_port01, Setup_blackbox01 added
|
||||
// 1.5.0 16-Apr-2014 5.3 Rules Ac_coherency01a and Ac_coherency02a deleted
|
||||
// 1.6.0 30-Apr-2014 5.3 Rule Clock_sync09 removed
|
||||
// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency
|
||||
// 1.8.0 21-Jul-2014 5.3.1 Enabled Ac_glitch03, allow_combo_logic
|
||||
// 1.8.1 08-Aug-2014 5.3.1 Removed Ac_conv05. Ac_conv04 description updated
|
||||
// 1.10.0 17-Dec-2014 5.4.1 Setup_req01 removed
|
||||
// 1.10.2 23-Feb-2015 5.4.1 Parameter cdc_reduce_pessimism=ignore_multi_domain added
|
||||
// Parameter reset_reduce_pessimism=remove_overlap added
|
||||
// Parameter sdc_generate_cfp added
|
||||
// Rule FalsePathSetup added
|
||||
// Rule Setup_library01 added
|
||||
// 1.11.0 11-Jun-2015 5.5.0 Rule parameter cdc_qualifier_depth added
|
||||
// 1.11.1 31-Aug-2015 5.5.1 Parameter fa_disable_sync_fifo=yes removed
|
||||
// 1.12.0 16-Nov-2016 2016.06-SP2 Rules Clock_info02 and Reset_info02 removed
|
||||
// 1.13.0 03-Feb-2017 2017.03 Added parameter report_common_reset
|
||||
// 1.14.0 26-Apr-2017 2017.03-SP1 Rules Clock_info05c, Clock_glitch05, Clock_info01, Reset_info01 added
|
||||
// Parameters check_multiclock_bbox, cdc_qualifier_depth, conv_sync_seq_depth, conv_sync_seq_depth_opt, clock_reduce_pessimism, allow_merged_qualifier added
|
||||
// Overloaded rule severity for rules Clock_sync05, Clock_sync06, Reset_sync02
|
||||
// Removed rules Reset_check10, Reset_info02, Clock_info02
|
||||
// 1.15.0 18-July-2017 2017.12 Rule Ac_glitch04, Clock_sync05a, Clock_sync06a added
|
||||
// Parameter conv_sync_as_src added
|
||||
// Parameter use_inferred_abstract_port added
|
||||
// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added
|
||||
//
|
||||
// Copyright Atrenta Inc, 2016. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
cdc_verify mixed
|
||||
*
|
||||
Clock Domain Crossing Verification
|
||||
*
|
||||
This step is used to verify all aspects of clock domain crossings; main CDC
|
||||
issues covered are:
|
||||
1- Metastability
|
||||
2- Data hold with regard to destination clock and enable
|
||||
3- Coherency problem on reconvergent crossings
|
||||
4- Functional correctness of FIFOs
|
||||
5- Ensure all synchronous resets follow convention specified by reset_sync_style
|
||||
constraint
|
||||
In this step any change that may affect the setup will also be monitored and
|
||||
any setup issues (e.g. converging clocks, missing clocks definition) will be
|
||||
reported.
|
||||
For faster CDC verification closure, it is recommended to address structural
|
||||
violations by running cdc_verify_struct prior to this step.
|
||||
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=clock-reset
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
-mixed //allow mixed language
|
||||
-enable_const_prop_thru_seq //allow to propagate beyond the sequential elements
|
||||
-use_advcdc_features //Run Advanced CDC Rules in restore mode
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
-enable_mux_sync=all //MUX Synchronization schemes
|
||||
-enable_and_sync=yes //Enables the AND Gate Synchronization Scheme
|
||||
-distributed_fifo=yes //Enables detection of FIFOs based on distributed memories
|
||||
-enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic
|
||||
-hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution
|
||||
-strict_sync_check=yes //Allows combinational logic between the source and destination flip-flops
|
||||
-fa_vcdfulltrace=allnets //Specifies the type of data that is to be dumped to the VCD file
|
||||
-fa_msgmode=all //Specifies the type of assertions
|
||||
-reset_reduce_pessimism=same_data_reset_flop,remove_overlap //Remove overlap between reset sync check and async reset (reset_sync02) rules
|
||||
-cdc_reduce_pessimism=mbit_macro,no_convergence_at_syncreset,no_convergence_at_enable,use_multi_arc,clock_crossing,no_unate_reconv,clock_on_ports,ignore_multi_domain //Let multi-domain source synchronizers will be recognized in Ac_sync but Ac_glitch03 will continue to report the issue.
|
||||
-sdc_generate_cfp=yes //Inferring cdc_false_path for asynchronous clocks in different domains
|
||||
-report_common_reset=yes //Reports the common reset source skipping buf/inv and MUX/combo gates acting as buffer
|
||||
-use_inferred_abstract_port=yes
|
||||
-conv_sync_as_src=yes
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Ac_clockperiod01 // Missing -period or -edge fields of the clock constraint defined in an SGDC file
|
||||
-overloadrules Ac_clockperiod01+severity=Error
|
||||
|
||||
-rules Ac_clockperiod02 //Clocks whose periods are rounded off by SpyGlass for lower design cycle for faster functional analysis
|
||||
|
||||
-rules Ac_clockperiod03 // Clocks with design cycles greater than the threshold value
|
||||
-overloadrules Ac_clockperiod03+severity=Error
|
||||
|
||||
-rules Clock_info03a // Reports unconstrained clock nets
|
||||
-overloadrules Clock_info03a+severity=Error
|
||||
|
||||
-rules Clock_info05 // MUX descriptions where two or more clock signals converge
|
||||
-overloadrules Clock_info05+severity=Error
|
||||
|
||||
## -rules Clock_info05a // Signals on which the set_case_analysis should be set to control MUXed clock selection
|
||||
-overloadrules Clock_info05a+severity=Error
|
||||
|
||||
-rules Clock_info05b // Combinational gates other than MUXes where two or more clock signals converge
|
||||
-overloadrules Clock_info05b+severity=Error
|
||||
|
||||
-rules Ac_resetvalue01 // Missing -value field of the reset constraint defined in an SGDC file
|
||||
-overloadrules Ac_resetvalue01+severity=Error
|
||||
|
||||
-rules Reset_info09a // Reports Unconstrained asynchronous reset nets
|
||||
-overloadrules Reset_info09a+severity=Error
|
||||
|
||||
-rules Clock_converge01 // Clocks whose multiple fan-outs converge
|
||||
-overloadrules Clock_converge01+severity=Error
|
||||
|
||||
-rules Ar_converge01 //Reports a reset signal whose multiple fan-outs converge
|
||||
|
||||
-rules Reset_check03 //Reset signals that are being used at both levels to set or reset flip-flops synchronously
|
||||
-overloadrules Reset_check03+severity=Error
|
||||
|
||||
-rules Reset_check11 //Asynchronous resets used as both active-high and active-low
|
||||
-overloadrules Reset_check11+severity=Error
|
||||
|
||||
-rules Reset_check12 // Flops that do not get active reset during power on reset
|
||||
-overloadrules Reset_check12+severity=Error
|
||||
|
||||
-rules Clock_info03b //Flip-flops,latches where the data pins are tied to a constant value
|
||||
|
||||
-rules Clock_info03c // Reports Flip-flops or latches where the clock/enable pin is set to a constant
|
||||
-overloadrules Clock_info03c+severity=Error
|
||||
|
||||
-rules Setup_port01 //Reports unconstrained ports summary for top design unit
|
||||
|
||||
-rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes
|
||||
|
||||
-rules Clock_check10 // Reports clocks being used as data
|
||||
|
||||
-rules Ac_initstate01 // Reports a valid state of the design from which the formal analysis would actually start
|
||||
|
||||
-rules Ar_syncrstactive01 // Polarity on synchronous reset usage mismatches with -active field in sync_reset_style constraint
|
||||
|
||||
-rules Ar_syncrstcombo01 // Combinational logic in synchronous reset path mismatches with -combo field in sync_reset_style constraint
|
||||
|
||||
-rules Ar_syncrstload01 // Load on synchronous reset less than the specified max load
|
||||
|
||||
-rules Ar_syncrstload02 // Load on synchronous reset exceeds the specified min load
|
||||
|
||||
-rules Ar_syncrstpragma01 // Pragma specification on synchronous reset usage mismatches with -pragma field in sync_reset_style constraint
|
||||
|
||||
-rules Ar_syncrstrtl01 // Reports if synchronous reset is not detected in condition of first if statement
|
||||
|
||||
-rules Ac_unsync01 // Asynchronous clock domain crossings for scalar signals that have at least one unsynchronized source
|
||||
|
||||
-rules Ac_unsync02 // Asynchronous clock domain crossings for vector signals having at least one unsynchronized source
|
||||
|
||||
-rules Clock_sync05 // Checks for multi-sample inputs
|
||||
-overloadrules Clock_sync05+severity=Error
|
||||
|
||||
-rules Clock_sync05a //Reports primary inputs (for which domain is auto-inferred using abstract_module constraint) sampled by multiple clock domains
|
||||
-rules Clock_sync06 // Checks for multi-transition outputs
|
||||
-overloadrules Clock_sync06+severity=Error
|
||||
|
||||
-rules Clock_sync06a // Reports primary outputs (for which domain is auto-inferred using abstract_module constraint) driven by multiple clock domain flip-flops or latches
|
||||
-rules Ar_unsync01 // Reports unsynchronized reset signals in the design
|
||||
|
||||
-rules Ar_asyncdeassert01 // Reports if reset signal is asynchronously de-asserted
|
||||
|
||||
-rules Reset_sync02 // Asynchronous resets used in a clock domain and generated in one of its asynchronous clock domains
|
||||
-overloadrules Reset_sync02+severity=Error
|
||||
|
||||
-rules Reset_sync04 //Asynchronous resets synchronized more than once in the same clock domain
|
||||
|
||||
-rules Ac_datahold01a // Reports synchronized data clock domain crossings where data can be unstable
|
||||
|
||||
-rules Ac_conv01 //same domain signals synchronized in same destination domain, converge after any number of sequential elements
|
||||
|
||||
-rules Ac_conv02 //same-domain signals synchronized in same destination domain and converge before sequential elements.
|
||||
|
||||
-rules Ac_conv03 // Convergence of synchronized signals from different source domains
|
||||
|
||||
-rules Ac_conv04 //For all control-bus clock domain crossings that do not converge, checks for uniform synchronization schemes and further checks gray encoding when formal is enabled
|
||||
|
||||
-rules Ac_coherency06 //Reports signals synchronized more than once in the same clock domain
|
||||
|
||||
-rules Ac_glitch03 // Reports clock domain crossings subject to glitches
|
||||
-allow_combo_logic=yes //allows combinational logic between crossings only if the logic is within the modules specified using this constraint.
|
||||
-rules Ac_glitch04 // Reports clock domain crossings subject to glitches
|
||||
|
||||
-rules Ac_cdc01a // Checks data loss from fast to slow multi-flop or sync-cell synchronized clock domain crossings
|
||||
|
||||
-rules Ac_crossing01 // Generate spreadsheet for Crossing Matrix view
|
||||
|
||||
-rules Ac_sync01 // Asynchronous clock domain crossings for scalar signals that have all the sources synchronized
|
||||
|
||||
-rules Ac_sync02 // Asynchronous clock domain crossings for vector signals that have all sources synchronized
|
||||
|
||||
-rules Ar_sync01 // Reports synchronized reset signals in the design
|
||||
|
||||
-rules Ar_syncdeassert01 // Reports if reset signal is synchronously de-asserted or not de-asserted at all
|
||||
|
||||
-rules Clock_info15 // Generates clock domain information for primary ports
|
||||
|
||||
-rules Setup_quasi_static01 // Reports likely quasi-static candidates in the design
|
||||
|
||||
-rules Ar_syncrst_setupcheck01 // Reports constant value on functional flops in synchronous reset deassert-mode
|
||||
|
||||
-rules Info_Case_Analysis // Constant propagation in schematic display
|
||||
|
||||
-rules Clock_info05c //Reports unconstrained MUXes which do not receive clocks in all its data inputs
|
||||
|
||||
-rules Clock_glitch05 //Flags asynchronous sources that converge with different domain clocks
|
||||
|
||||
-check_multiclock_bbox=yes //Clock domain crossing involving the unconstrained pins of black-box instances on destination side and receiving multiple clock are ignored
|
||||
-cdc_qualifier_depth=3 //Default is infinite. This leads to some wrong qualifiers
|
||||
-conv_sync_seq_depth=1 //Default to only checking Ac_conv01 to 1 flop. User can override to go deeper
|
||||
-conv_sync_seq_depth_opt=yes //Optimizes Ac_conv runtime when depth=1
|
||||
-clock_reduce_pessimism=latch_en,mux_sel_derived,check_enable_for_glitch,ignore_same_domain
|
||||
-allow_merged_qualifier=strict
|
||||
|
||||
-rules Clock_info01 //Reports likely clock signals
|
||||
|
||||
-rules Reset_info01 //Reports likely asynchronous and synchronous preset and clear signals
|
||||
|
||||
-rules FalsePathSetup //Cases where cdc_false_path constraint is not used by any crossing in the design
|
||||
|
||||
-rules Setup_library01 //Reports incomplete definition of library pins for CDC
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,85 +0,0 @@
|
||||
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<blockquote>
|
||||
<a name="wp1131532"> </a><h2 class="pHeading1">
|
||||
cdc_verify
|
||||
</h2>
|
||||
<a name="wp1131567"> </a><p class="pBody">
|
||||
The aim of this goal is to verify all aspects of clock domain crossings. Review and fix each category of CDC problems separately. The violations can be debugged and fixed in the following order
|
||||
</p>
|
||||
<div class="pSmartList1"><ol type="1" class="pSmartList1">
|
||||
<a name="wp1131568"> </a><div class="pSmartList1"><li>Ensure that the setup is clean: analyze and fix violations reported by the following rules</li></div>
|
||||
<a name="wp1131740"> </a><p class="pBodyRelative">
|
||||
Clock_info03a, Clock_info03b, Clock_info03c, Clock_info05, Clock_info05b, Clock_converge01, Ar_converge01, Reset_info09a, Ac_resetvalue01, Ac_clockperiod01, Ac_clockperiod02, Ac_clockperiod03, Clock_info15, Setup_port01, Setup_blackbox01, Reset_check03, Reset_check10, Reset_check11, Reset_check12, Ar_syncrstactive01, Ar_syncrstcombo01, Ar_syncrstload01, Ar_syncrstload02, Ar_syncrstpragma01, Ar_syncrstrtl01, FalsePathSetup, Setup_library01
|
||||
</p>
|
||||
<a name="wp1131741"> </a><div class="pSmartList1"><li>Ensure that the design has been properly initialized: Review Ac_initstate01 to ensure at least 80% of flops are initialized and uninitialized flops are not important for functional verification (e.g. sometimes memories are not initialized and are initialized during the execution of the design).</li></div>
|
||||
<a name="wp1131573"> </a><div class="pSmartList1"><li>Analyze and fix the unsynchronized crossings reported by Ac_unsync01 and Ac_unsync02 rules</li></div>
|
||||
<a name="wp1131575"> </a><div class="pSmartList1"><li>Analyze and fix other clock and reset synchronization issues reported by the following rules:</li></div>
|
||||
<a name="wp1131576"> </a><p class="pBodyRelative">
|
||||
Clock_sync05, Clock_sync06, Ar_unsync01, Ar_asyncdeassert01, Reset_sync02, Reset_sync04
|
||||
</p>
|
||||
<a name="wp1131578"> </a><div class="pSmartList1"><li>Analyze and fix convergence issues reported by following rules</li></div>
|
||||
<a name="wp1131579"> </a><p class="pBodyRelative">
|
||||
Ac_conv01, Ac_conv02, Ac_conv03, Ac_conv04, Ac_coherency06
|
||||
</p>
|
||||
<a name="wp1131581"> </a><div class="pSmartList1"><li>Ensure that crossings functionality is correct: Analyze and fix following rules </li></div>
|
||||
<a name="wp1131582"> </a><p class="pBodyRelative">
|
||||
Ac_cdc01a, Ac_datahold01a
|
||||
</p>
|
||||
</ol></div>
|
||||
|
||||
|
||||
|
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</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
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|
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|
||||
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|
||||
@ -1,244 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : cdc_verify_struct
|
||||
// Version: 1.14.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date SG Ver Comments
|
||||
// 1.0.0 18-Feb-2013 5.0 Initial version
|
||||
// 1.1.0 26-Apr-2013 5.1 Rules Ac_datahold01a, Ac_cdc01a, Ac_cdc08 removed
|
||||
// Rule Ar_syncrst_setupcheck01 added
|
||||
// Parameter enable_handshake removed
|
||||
// 1.2.0 06-Aug-2013 5.1.1 Rules Ac_handshake01 and Ac_handshake02 removed
|
||||
// 1.3.0 04-Oct-2013 5.2 Rule Clock_check10 added
|
||||
// Rules Ac_coherency01a, Ac_coherency02a added
|
||||
// 1.4.0 12-Feb-2014 5.2.1 Clock_info18, Ac_fifo01, enable_fifo removed
|
||||
// Ar_converge01, Setup_req01, Ac_conv04, Ac_conv05, Ac_coherency06, Ac_abstract_validation01, SGDC_abstract_mapping01, validate_reduce_pessimism, abstract_validate_express,Setup_port01,Setup_blackbox01 added
|
||||
// 1.5.0 16-Apr-2014 5.3 Rules Ac_coherency01a and Ac_coherency02a deleted
|
||||
// 1.6.0 30-Apr-2014 5.3 Rule Clock_sync09 removed
|
||||
// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency
|
||||
// 1.8.0 21-Jul-2014 5.3.1 Enabled Ac_glitch03, allow_combo_logic
|
||||
// 1.8.1 08-Aug-2014 5.3.1 Removed Ac_conv05. Ac_conv04 description updated
|
||||
// 1.10.0 17-Dec-2014 5.4.1 Setup_req01 removed
|
||||
// 1.10.2 23-Feb-2015 5.4.1 Parameter cdc_reduce_pessimism=ignore_multi_domain added
|
||||
// Parameter reset_reduce_pessimism=remove_overlap added
|
||||
// Parameter sdc_generate_cfp added
|
||||
// Rule FalsePathSetup added
|
||||
// Rule Setup_library01 added
|
||||
// Rule Ac_clockperiod01 removed
|
||||
// Rule Ac_clockperiod02 removed
|
||||
// 1.11.0 11-Jun-2015 5.5.0 Rule parameter cdc_qualifier_depth added
|
||||
// 1.12.0 16-Nov-2016 2016.06-SP2 Rules Clock_info02 and Reset_info02 removed
|
||||
// 1.13.0 03-Feb-2017 2017.03 Added parameter report_common_reset
|
||||
// 1.14.0 26-Apr-2017 2017.03-SP1 Rule Ac_abstract_validation01 removed and Ac_abstract_validation02 added
|
||||
// Rules Clock_info05c, Clock_glitch05, Clock_info01, Reset_info01 added
|
||||
// Parameters autofix_abstract_port, check_multiclock_bbox, cdc_qualifier_depth, conv_sync_seq_depth, conv_sync_seq_depth_opt, clock_reduce_pessimism, allow_merged_qualifier added
|
||||
// Overloaded rule severity for rules Clock_sync05, Clock_sync06, Reset_sync02
|
||||
// Removed rules Ac_clockperiod01, Ac_clockperiod02, Ac_clockperiod03, Reset_check10, Reset_info02, Clock_info02
|
||||
// 1.15.0 18-July-2017 2017.12 Rule Ac_glitch04, Clock_sync05a, Clock_sync06a added
|
||||
// Parameter conv_sync_as_src added
|
||||
// Parameter use_inferred_abstract_port added
|
||||
// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added
|
||||
//
|
||||
// Copyright Atrenta Inc, 2016. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
cdc_verify_struct mixed
|
||||
*
|
||||
Clock Domain Crossing Verification
|
||||
*
|
||||
This step is used to verify all aspects of clock domain crossings; main CDC
|
||||
issues covered are:
|
||||
1- Metastability
|
||||
2- Coherency problem on reconvergent crossings
|
||||
3- Ensure all synchronous resets follow convention specified by reset_sync_style
|
||||
constraint
|
||||
In this step any change that may affect the setup will also be monitored and
|
||||
any setup issues (e.g. converging clocks, missing clocks definition) will be
|
||||
reported.
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=clock-reset
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
-mixed //allow mixed language
|
||||
-enable_const_prop_thru_seq //allow to propagate beyond the sequential elements
|
||||
-use_advcdc_features //Run Advanced CDC Rules in restore mode
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
-enable_mux_sync=all //MUX Synchronization schemes
|
||||
-enable_and_sync=yes //Enables the AND Gate Synchronization Scheme
|
||||
-distributed_fifo=yes //Enables detection of FIFOs based on distributed memories
|
||||
-fa_disable_sync_fifo=yes //Specifies whether functional analysis should be performed on synchronous FIFO structures
|
||||
-enable_debug_data=yes //Enables annotation of debug information, such as clock, reset, quasi_static signals, and domain information on nets in the schematic
|
||||
-hier_wild_card=no //Specifies the format of specifying hierarchies by using wildcard expressions in all the constraints used by the SpyGlass CDC solution
|
||||
-strict_sync_check=yes //Allows combinational logic between the source and destination flip-flops
|
||||
-fa_vcdfulltrace=allnets //Specifies the type of data that is to be dumped to the VCD file
|
||||
-fa_msgmode=none //Specifies the type of assertions
|
||||
-reset_reduce_pessimism=same_data_reset_flop,remove_overlap //Remove overlap between reset sync check and async reset (reset_sync02) rules
|
||||
-sdc_generate_cfp=yes //Inferring cdc_false_path for asynchronous clocks in different domains
|
||||
-cdc_reduce_pessimism=mbit_macro,no_convergence_at_syncreset,no_convergence_at_enable,use_multi_arc,clock_crossing,no_unate_reconv,clock_on_ports,ignore_multi_domain //Let multi-domain source synchronizers will be recognized in Ac_sync but Ac_glitch03 will continue to report the issue.
|
||||
-report_common_reset=yes //Reports the common reset source skipping buf/inv and MUX/combo gates acting as buffer
|
||||
-use_inferred_abstract_port=yes
|
||||
-conv_sync_as_src=yes
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
#-rules Ac_clockperiod03 // Clocks with design cycles greater than the threshold value
|
||||
|
||||
-rules Clock_info03a // Reports unconstrained clock nets
|
||||
-overloadrules Clock_info03a+severity=Error
|
||||
|
||||
-rules Clock_info05 // MUX descriptions where two or more clock signals converge
|
||||
-overloadrules Clock_info05+severity=Error
|
||||
|
||||
## -rules Clock_info05a // Signals on which the set_case_analysis should be set to control MUXed clock selection
|
||||
-overloadrules Clock_info05a+severity=Error
|
||||
|
||||
-rules Clock_info05b // Combinational gates other than MUXes where two or more clock signals converge
|
||||
-overloadrules Clock_info05b+severity=Error
|
||||
|
||||
-rules Ac_resetvalue01 // Missing -value field of the reset constraint defined in an SGDC file
|
||||
-overloadrules Ac_resetvalue01+severity=Error
|
||||
|
||||
-rules Reset_info09a // Reports Unconstrained asynchronous reset nets
|
||||
-overloadrules Reset_info09a+severity=Error
|
||||
|
||||
-rules Clock_converge01 // Clocks whose multiple fan-outs converge
|
||||
-overloadrules Clock_converge01+severity=Error
|
||||
|
||||
-rules Ar_converge01 //Reports a reset signal whose multiple fan-outs converge
|
||||
|
||||
-rules Reset_check03 //Reset signals that are being used at both levels to set or reset flip-flops synchronously
|
||||
-overloadrules Reset_check03+severity=Error
|
||||
|
||||
#-rules Reset_check10 // Asynchronous resets used as non-reset signals
|
||||
#-overloadrules Reset_check10+severity=Error
|
||||
|
||||
-rules Reset_check11 //Asynchronous resets used as both active-high and active-low
|
||||
-overloadrules Reset_check11+severity=Error
|
||||
|
||||
-rules Reset_check12 // Flops that do not get active reset during power on reset
|
||||
-overloadrules Reset_check12+severity=Error
|
||||
|
||||
-rules Clock_info03b //Flip-flops,latches where the data pins are tied to a constant value
|
||||
|
||||
-rules Clock_info03c // Reports Flip-flops or latches where the clock/enable pin is set to a constant
|
||||
-overloadrules Clock_info03c+severity=Error
|
||||
|
||||
-rules Setup_port01 //Reports unconstrained ports summary for top design unit
|
||||
|
||||
-rules Setup_blackbox01 //Reports unconstrained pins summary for black-boxes
|
||||
|
||||
-rules Clock_check10 // Reports clocks being used as data
|
||||
|
||||
-rules Ac_initstate01 // Reports a valid state of the design from which the formal analysis would actually start
|
||||
|
||||
-rules Ar_syncrstactive01 // Polarity on synchronous reset usage mismatches with -active field in sync_reset_style constraint
|
||||
|
||||
-rules Ar_syncrstcombo01 // Combinational logic in synchronous reset path mismatches with -combo field in sync_reset_style constraint
|
||||
|
||||
-rules Ar_syncrstload01 // Load on synchronous reset less than the specified max load
|
||||
|
||||
-rules Ar_syncrstload02 // Load on synchronous reset exceeds the specified min load
|
||||
|
||||
-rules Ar_syncrstpragma01 // Pragma specification on synchronous reset usage mismatches with -pragma field in sync_reset_style constraint
|
||||
|
||||
-rules Ar_syncrstrtl01 // Reports if synchronous reset is not detected in condition of first if statement
|
||||
|
||||
-rules Ac_unsync01 // Asynchronous clock domain crossings for scalar signals that have at least one unsynchronized source
|
||||
|
||||
-rules Ac_unsync02 // Asynchronous clock domain crossings for vector signals having at least one unsynchronized source
|
||||
|
||||
-rules Clock_sync05 // Checks for multi-sample inputs
|
||||
-overloadrules Clock_sync05+severity=Error
|
||||
|
||||
-rules Clock_sync05a //Reports primary inputs (for which domain is auto-inferred using abstract_module constraint) sampled by multiple clock domains
|
||||
-rules Clock_sync06 // Checks for multi-transition outputs
|
||||
-overloadrules Clock_sync06+severity=Error
|
||||
|
||||
-rules Clock_sync06a // Reports primary outputs (for which domain is auto-inferred using abstract_module constraint) driven by multiple clock domain flip-flops or latches
|
||||
-rules Ar_unsync01 // Reports unsynchronized reset signals in the design
|
||||
|
||||
-rules Ar_asyncdeassert01 // Reports if reset signal is asynchronously de-asserted
|
||||
|
||||
-rules Reset_sync02 // Asynchronous resets used in a clock domain and generated in one of its asynchronous clock domains
|
||||
-overloadrules Reset_sync02+severity=Error
|
||||
|
||||
-rules Reset_sync04 //Asynchronous resets synchronized more than once in the same clock domain
|
||||
|
||||
-rules Ac_conv01 //same domain signals synchronized in same destination domain, converge after any number of sequential elements
|
||||
|
||||
-rules Ac_conv02 //same-domain signals synchronized in same destination domain and converge before sequential elements.
|
||||
|
||||
-rules Ac_conv03 // Convergence of synchronized signals from different source domains
|
||||
|
||||
-rules Ac_conv04 //For all control-bus clock domain crossings that do not converge, checks for uniform synchronization schemes and further checks gray encoding when formal is enabled
|
||||
|
||||
-rules Ac_coherency06 //Reports signals synchronized more than once in the same clock domain
|
||||
|
||||
-rules Ac_glitch03 // Reports clock domain crossings subject to glitches
|
||||
-allow_combo_logic=yes //allows combinational logic between crossings only if the logic is within the modules specified using this constraint.
|
||||
-rules Ac_glitch04 //Reports clock domain crossings subject to glitches
|
||||
|
||||
-rules Ac_crossing01 // Generate spreadsheet for Crossing Matrix view
|
||||
|
||||
-rules Ac_sync01 // Asynchronous clock domain crossings for scalar signals that have all the sources synchronized
|
||||
|
||||
-rules Ac_sync02 // Asynchronous clock domain crossings for vector signals that have all sources synchronized
|
||||
|
||||
-rules Ar_sync01 // Reports synchronized reset signals in the design
|
||||
|
||||
-rules Ar_syncdeassert01 // Reports if reset signal is synchronously de-asserted or not de-asserted at all
|
||||
|
||||
-rules Clock_info15 // Generates clock domain information for primary ports
|
||||
|
||||
-rules Setup_quasi_static01 // Reports likely quasi-static candidates in the design
|
||||
|
||||
-rules Ar_syncrst_setupcheck01 // Reports constant value on functional flops in synchronous reset deassert-mode
|
||||
|
||||
-rules Info_Case_Analysis // Constant propagation in schematic display
|
||||
|
||||
-rules Ac_abstract_validation02 //Reports block abstraction mismatch with top level design
|
||||
|
||||
-rules Clock_info05c //Reports unconstrained MUXes which do not receive clocks in all its data inputs
|
||||
|
||||
-rules Clock_glitch05 //Flags asynchronous sources that converge with different domain clocks
|
||||
|
||||
-rules Clock_info01 //Reports likely clock signals
|
||||
|
||||
-rules Reset_info01 //Reports likely asynchronous and synchronous preset and clear signals
|
||||
|
||||
-validate_reduce_pessimism=all //ignore reporting on the block ports that are hanging, or have a constant or quasi static signal reaching on them
|
||||
-abstract_validate_express=no //Enables low noise and low effort validation checks for hierarchical SoC flow
|
||||
-autofix_abstract_port=no //Used to turn on|off autofix feature
|
||||
-check_multiclock_bbox=yes //Clock domain crossing involving the unconstrained pins of black-box instances on destination side and receiving multiple clock are ignored
|
||||
-cdc_qualifier_depth=3 //Default is infinite. This leads to some wrong qualifiers
|
||||
-conv_sync_seq_depth=1 //Default to only checking Ac_conv01 to 1 flop. User can override to go deeper
|
||||
-conv_sync_seq_depth_opt=yes //Optimizes Ac_conv runtime when depth=1
|
||||
-clock_reduce_pessimism=latch_en,mux_sel_derived,check_enable_for_glitch,ignore_same_domain
|
||||
-allow_merged_qualifier=strict
|
||||
|
||||
-rules SGDC_abstract_mapping01 //Reports clock mapping of an abstracted instance
|
||||
|
||||
-rules FalsePathSetup //Cases where cdc_false_path constraint is not used by any crossing in the design
|
||||
|
||||
-rules Setup_library01 //Reports incomplete definition of library pins for CDC
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,80 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="06/10/10 14:48:47" />
|
||||
<title>cdc_verify_struct</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131620"> </a><h2 class="pHeading1">
|
||||
cdc_verify_struct
|
||||
</h2>
|
||||
<a name="wp1131786"> </a><p class="pBody">
|
||||
The aim of this goal is to verify structural aspects of clock domain crossings. Review and fix each category of CDC problems separately. The violations can be debugged and fixed in the following order:
|
||||
</p>
|
||||
<div class="pSmartList1"><ol type="1" class="pSmartList1">
|
||||
<a name="wp1131787"> </a><div class="pSmartList1"><li>Ensure that the setup is clean: analyze and fix violations reported by the following rules:</li></div>
|
||||
<a name="wp1131641"> </a><p class="pBodyRelative">
|
||||
Clock_info03a, Clock_info03b, Clock_info03c, Clock_info05, Clock_info05b, Clock_converge01, Ar_converge01, Reset_info09a, FalsePathSetup, Setup_library01, Ac_resetvalue01, Clock_info15, Setup_port01, Setup_blackbox01, Reset_check03, Reset_check11, Reset_check12, Ar_syncrstactive01 Ar_syncrstcombo01 Ar_syncrstload01 Ar_syncrstload02 Ar_syncrstpragma01 Ar_syncrstrtl01 Clock_info05c Clock_glitch05 Clock_info01 Reset_info01
|
||||
</p>
|
||||
<a name="wp1131643"> </a><div class="pSmartList1"><li>Analyze and fix the unsynchronized crossings reported by Ac_unsync01 and Ac_unsync02 rules</li></div>
|
||||
<a name="wp1131645"> </a><div class="pSmartList1"><li>Analyze and fix other clock and reset synchronization issues reported by the following rules:</li></div>
|
||||
<a name="wp1131646"> </a><p class="pBodyRelative">
|
||||
Clock_sync05, Clock_sync06, Ar_unsync01, Ar_asyncdeassert01, Reset_sync02, Reset_sync04
|
||||
</p>
|
||||
<a name="wp1131648"> </a><div class="pSmartList1"><li>Analyze and fix convergence issues reported by the following rules:</li></div>
|
||||
<a name="wp1131649"> </a><p class="pBodyRelative">
|
||||
Ac_conv01, Ac_conv02, Ac_conv03, Ac_conv04, Ac_coherency06, Ac_abstract_validation02, SGDC_abstract_mapping01
|
||||
</p>
|
||||
</ol></div>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
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|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
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|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,117 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : clock_reset_integrity
|
||||
// Version: 1.14.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date SG Ver Comments
|
||||
// 1.0.0 18-Feb-2013 5.0 Initial version
|
||||
// 1.4.0 12-Feb-2014 5.2.1 Ar_converge01 added
|
||||
// 1.7.0 30-Apr-2014 5.3.0 Guidware 2.0 Content Consistency
|
||||
// 1.10.1 22-Dec-2014 5.4.1 Adding starc2005 policy since STARC05-1.4.3.2 requires it
|
||||
// 1.12.0 18-Nov-2015 5.6.0 Parameter handle_combo_arc=yes added
|
||||
// 1.13.0 26-Apr-2017 2017.03 Removed timing policy and corresponding rule ClockEnableRace
|
||||
//
|
||||
//1.14.0 13-July-2017 2017.12 Overloaded rule severity for Reset_check12
|
||||
// 1.17.0 22-Jan-2018 2017.12 Option use_advcdc_features added
|
||||
// 1.18.0 04-Dec-2018 2018.09 QualifierSetup rule removed due to unneccessary noise STAR #9001291972
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
clock_reset_integrity mixed
|
||||
*
|
||||
Sanity check of Clocks and Resets
|
||||
*
|
||||
This step ensures that clocks and resets trees are properly designed and they
|
||||
are free of glitches, races, and other hazards.
|
||||
Note that most of the checks require the clocks and resets to be defined. If
|
||||
you do not have the clocks and resets definitions, you must run the setup for
|
||||
this step to define them before proceeding with verification.
|
||||
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=clock-reset
|
||||
// -policy=starc2005
|
||||
// -policy morelint
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
-mixed //allow mixed language
|
||||
-use_advcdc_features //Run Advanced CDC Rules in restore mode
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
-handle_combo_arc=yes //propagate clocks through lib cells
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Clock_info05b //detect clock signals converging on a combinational gate other than a MUX
|
||||
|
||||
-rules Clock_check01 //detect unexpected cells, such as latch, tristate, or XOR/XNOR gates in a clock tree
|
||||
|
||||
-rules Clock_check04 //Reports the usage of both the edges (positive and negative) of a clock
|
||||
|
||||
-rules Reset_check01 //Reports reset signals that are used in a different mode from their respective synthesis pragmas
|
||||
|
||||
-rules Reset_check02 //Reports latches, tristate signals, or XOR/XNOR gates in a reset tree
|
||||
|
||||
-rules Reset_check03 //Reports synchronous reset signals that are used as active high as well as active low
|
||||
|
||||
-rules Reset_check04 //Reports reset signals that are used asynchronously as well as synchronously for different flip-flops
|
||||
|
||||
-rules Reset_check06 //Reports high fan-out reset nets that are not driven by placeholder cells
|
||||
|
||||
-rules Reset_check07 //Reports asynchronous reset pins driven by a combinational logic
|
||||
|
||||
-rules Clock_Reset_info01 //Generates the Clock-Reset Matrix
|
||||
|
||||
-rules Clock_glitch02 //Reports clocks that are gated without latching their enable signal properly
|
||||
-overloadrules Clock_glitch02+severity=Warning
|
||||
|
||||
-rules Clock_glitch03 //Reports clock signals that pass through a MUX and reconverge back on the same MUX
|
||||
-overloadrules Clock_glitch03+severity=Warning
|
||||
|
||||
-rules Clock_glitch04 //Reports flip-flops that converge on a clock pin of a flip-flop through a combinational logic
|
||||
-overloadrules Clock_glitch04+severity=Warning
|
||||
|
||||
-rules Clock_Reset_check02 //Reports potential race conditions between flip-flop output and its clock/reset pin
|
||||
|
||||
-rules Clock_Reset_check01 //Reports unwanted cells found in clock or reset networks
|
||||
|
||||
-rules Clock_Reset_check03 //Reports potential race condition between flip-flop clock and reset pins
|
||||
|
||||
-rules Clock_converge01 //Reports the clock signal for which multiple fan-outs converge
|
||||
|
||||
-rules Ar_converge01 //Reports a reset signal whose multiple fan-outs converge
|
||||
|
||||
-rules Info_Case_Analysis //Constant propagation in schematic display
|
||||
|
||||
// -rules STARC05-1.4.3.2
|
||||
//-overloadrules STARC05-1.4.3.2+severity=Warning
|
||||
|
||||
// -rules Clock_check02 # high fanout clocks needed only for netlist audit
|
||||
|
||||
// -rules Clock_check03 # bus bits used as clocks not a design problem
|
||||
// -rules ResetFlop-ML # All the flip-flops should have either synchronous set/reset or asynchronous set/reset
|
||||
|
||||
// -rules Reset_check12 # Reports flops that do not receive active reset when specified reset is active
|
||||
-overloadrules Reset_check12+severity=Error+msgLabel=NORMAL_WARNING
|
||||
-overloadrules Reset_check12+severity=Info+msgLabel=CORNER_WARNING
|
||||
|
||||
-ignorerules QualifierSetup //Removed due to unneccessary noise
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,79 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="06/10/10 14:48:47" />
|
||||
<title>clock_reset_integrity</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131473"> </a><h2 class="pHeading1">
|
||||
clock_reset_integrity
|
||||
</h2>
|
||||
<a name="wp1131492"> </a><p class="pBody">
|
||||
The aim of this goal is to check the integrity of clock and reset logic in a design. The violations can be analyzed in the following order:
|
||||
</p>
|
||||
<div class="pSmartList1"><ol type="1" class="pSmartList1">
|
||||
<a name="wp1131493"> </a><div class="pSmartList1"><li>Analyze and fix basic clock issues reported by the following rules:</li></div>
|
||||
<a name="wp1131494"> </a><p class="pBodyRelative">
|
||||
Clock_check01, Clock_check04, Clock_info05b, Clock_converge01, Ar_converge01
|
||||
</p>
|
||||
<a name="wp1131496"> </a><div class="pSmartList1"><li>Analyze and fix race and glitch issues reported by the following rules:</li></div>
|
||||
<a name="wp1131497"> </a><p class="pBodyRelative">
|
||||
Clock_glitch02, Clock_glitch03, Clock_glitch04, Clock_Reset_check01, Clock_Reset_check02, Clock_Reset_check03
|
||||
</p>
|
||||
<a name="wp1131499"> </a><div class="pSmartList1"><li>Analyze and fix basic issues in reset logic reported by the following rules:</li></div>
|
||||
<a name="wp1131500"> </a><p class="pBodyRelative">
|
||||
Reset_check01, Reset_check02, Reset_check03, Reset_check04, Reset_check06, Reset_check07
|
||||
</p>
|
||||
</ol></div>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,94 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare3.0-EarlyAdopter Goal File
|
||||
//
|
||||
// Goal Name : connectivity_verification
|
||||
// Version : 5.5.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 5.5.0 18-Jun-2015 Initial version
|
||||
//
|
||||
// Copyright Atrenta Inc, 2017. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
connectivity_verification
|
||||
*
|
||||
Easy capture of connectivity inten across IPs/SoCs and static checks to
|
||||
suppliment simulation based verification
|
||||
*
|
||||
Easy Capture of Connectivity-Intent across IP/SoC
|
||||
|
||||
1. Compact & portable constraints
|
||||
2. Verify 1:1, 1:many, many:1 connections
|
||||
3. Checking for illegal conditions
|
||||
4. Conditional connectivity
|
||||
5. Validate design methodology consistency across blocks and reuse at SoC level
|
||||
|
||||
Static Checks Supplements Simulation Based Verification
|
||||
|
||||
1. Fast performance to quickly find basic connectivity bugs
|
||||
2. Supports regression use model
|
||||
3. Violations clearly state the failure root-cause
|
||||
4. GUI based design analysis
|
||||
|
||||
For more details about this goal, please refer to the
|
||||
SpyGlass_ConnectivityVerify_Rules_Reference.pdf file in the doc
|
||||
subdirectory of your SpyGlass installation
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=dft_dsm,dft
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Soc_01 // Expected node value must be achieved
|
||||
|
||||
-rules Soc_02 // Paths between user specified nodes must exist
|
||||
|
||||
-rules Soc_07 // Structure between user specified nodes exists
|
||||
|
||||
-rules Soc_08 // Paths between user specified nodes exists or not
|
||||
|
||||
-rules Soc_09 // Path between user specified nodes must not exist
|
||||
|
||||
-rules Soc_10 // Specific value on user specified nodes must not exist
|
||||
|
||||
-rules Soc_11 // Node must satisfy the specified constraint message tag expression
|
||||
|
||||
-rules Soc_12 // Node must not have the specified constraint message tag expression
|
||||
|
||||
-rules Atspeed_21 // Check required pulse pattern at specified node
|
||||
|
||||
-rules Soc_01_Info // Expected node value is achieved
|
||||
|
||||
-rules Soc_02_Info // Connection between user specified nodes exists
|
||||
|
||||
-rules Soc_07_Info // Structure between user specified nodes exists
|
||||
|
||||
-rules Soc_04 // Show design state for a given tag
|
||||
|
||||
-rules Info_Atspeed_21 // Expected pulse pattern at specified node is achieved
|
||||
|
||||
-rules Info_testmode // Display testmode simulation results
|
||||
|
||||
-rules Diagnose_testmode // Display instances that blocks testmode propagation
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,10 +0,0 @@
|
||||
At RTL stage, the user may have two kind of issues
|
||||
1) Generate SDC from scratch
|
||||
2) Have the ability to check the correctness, consistency and completeness of the constraint to factilitate synthesis. This includes
|
||||
|
||||
* Consistency of Clocks and Generated clock
|
||||
* Overwritten or Duplicate Constraints
|
||||
* Consistency of Input/Output delays, clock latency, clock uncertainty
|
||||
* Analysis of Feedthrough paths
|
||||
* Verify structural connectivity of exceptions
|
||||
* Compare two SDCs for the same design
|
||||
@ -1,41 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : sdc_abstract
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++
|
||||
sdc_abstract
|
||||
*
|
||||
Generate Abstract Port for a design
|
||||
*
|
||||
Generates the abstract port for a design
|
||||
|
||||
For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.
|
||||
=cut+++++++++++
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=constraints
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
-block_abstract //for block abstraction
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
-rules CONS_abstract01 // rule that generate abstract port for a design
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
<html>
|
||||
<head>
|
||||
<h1>
|
||||
SDC Abstract
|
||||
</h1>
|
||||
</head>
|
||||
<body>
|
||||
<p>The purpose of this Goal is to generate abstract port for a design.
|
||||
The abstracted view can be used in verifying the timing at system level.</p>
|
||||
<p>The abstraction of the block is performed in correlation with the SDC
|
||||
constraints specified through sdc_data constraints. All such sdc_data constraints are processed and corresponding abstract_port constraints generated by the rule. The mode field of the abstract_port constraint specifies the corresponding sdc_data constraint. These constraints are output into sgdc file. The sgdc file path is highlighted in the message given by the rule.</p>
|
||||
</body>
|
||||
</html>
|
||||
|
||||
@ -1,121 +0,0 @@
|
||||
##########################################################################
|
||||
# SpyGlass Constraints Methodology
|
||||
#
|
||||
# Version: 1.2
|
||||
#
|
||||
# Revision History:
|
||||
# Ver Date Comments
|
||||
# 1.0 18-Jun-2008 Initial version
|
||||
# 1.1 28-Jul-2008 Fixed documentation issues and incorrect headers
|
||||
# (31071)
|
||||
# 1.2 23-Dec-2008 Fixed incorrect use of parameters (35516)
|
||||
#
|
||||
# Copyright Atrenta Inc, 2008. All rights reserved.
|
||||
##########################################################################
|
||||
# This is the setup file for SDC Validation
|
||||
##########################################################################
|
||||
##########################################################################
|
||||
# Register Variables to be used in the script here
|
||||
##########################################################################
|
||||
# Variable to check if user has SGDC file that he wants to use
|
||||
register_variable Q_ASK_FOR_SGDC 0
|
||||
# Variable to check if user has sdc file and no sgdc file
|
||||
register_variable Q_ASK_FOR_SDC 0
|
||||
#variable for sdc file name
|
||||
register_variable Q_SDC_FILE ""
|
||||
#variable for Last Setup
|
||||
register_variable Q_LAST_SETUP 0
|
||||
#Ask for current_design
|
||||
register_variable Q_CURRENT_DESIGN ""
|
||||
# Check if File Exists
|
||||
register_variable Q_FILE_EXISTS 0
|
||||
# Global SGDC File Name - Eventually to be use tagging
|
||||
register_variable Q_GLOBAL_SGDC "$PRJFILES_DIR/constraints.sgdc"
|
||||
|
||||
set_property -show_index
|
||||
set_property -hide_step_numbering
|
||||
|
||||
sgsSet Q_FILE_EXISTS 0
|
||||
get_property system.fileExists $Q_GLOBAL_SGDC -result_variable Q_FILE_EXISTS
|
||||
sgsIf { $Q_FILE_EXISTS == 1 } {
|
||||
set_header_state "Configure SpyGlass Design Constraint File" complete
|
||||
}
|
||||
|
||||
set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar
|
||||
sgsIf { $Q_FILE_EXISTS == 1 } {
|
||||
create_form -label "CONFIGURE LAST SETUP" {
|
||||
get_bool -text "A SGDC file from previous setup was detected. Do you want to use the last setup?" -result_variable Q_LAST_SETUP -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 }
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Analyze_the_Flavor_of_SDC.htm
|
||||
}
|
||||
} sgsElse {
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Analyze_the_Flavor_of_SDC.htm
|
||||
}
|
||||
set_header_state "Before You Start" complete
|
||||
|
||||
set_property -step_header "Configure SpyGlass Design Constraint File"
|
||||
sgsIf { $Q_LAST_SETUP == 0} {
|
||||
create_form -label "CONFIGURE SGDC FILE" {
|
||||
get_bool -text "Do you have a SGDC file?" -result_variable Q_ASK_FOR_SGDC -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 }
|
||||
get_bool -text "Do you have a SDC file" -result_variable Q_ASK_FOR_SDC -auto_proceed -style radio -geometry { -side bottom -expand 0 }
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
}
|
||||
set_property -disable_next_button
|
||||
sgsIf { ( $Q_ASK_FOR_SGDC == 1 ) && ( $Q_ASK_FOR_SDC == 1 ) } {
|
||||
show_text "<b>You have to either specify SGDC file(with sdc_data refering to SDC file) or a SDC file which will enable spyglass to automatically create SGDC file for you. Please click back and select one of them. If you select no for both, setup will create a boilerplate SGDC file for you to populate.</b>"
|
||||
}
|
||||
|
||||
sgsIf { $Q_ASK_FOR_SGDC == 1 } {
|
||||
set_property -enable_next_button
|
||||
get_file -type {"SGDC Files" "*.sgdc"} -fileExt { "SGDC Files" "*.sgdc" } -result_variable Q_SGDC_FILE -text "Please select the SGDC file"
|
||||
sgsExec { /bin/cp {get_variable $Q_SGDC_FILE } { get_variable $Q_GLOBAL_SGDC } }
|
||||
set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
} sgsElse {
|
||||
sgsIf {$Q_ASK_FOR_SDC == 1 } {
|
||||
set_property -enable_next_button
|
||||
create_form -label "CONFIGURE SDC FILE" {
|
||||
get_file -type { "SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE -text "Please select the SDC file"
|
||||
set_sgdc_curr_design -text "Enter Current Design" -result_variable Q_CURRENT_DESIGN
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
#get_property console.top -result_variable Q_CURRENT_DESIGN
|
||||
#set_sgdc_curr_design -text "Please select the Top Design Unit" -result_variable Q_CURRENT_DESIGN
|
||||
#get_string -text "Enter Current Design" -result_variable Q_CURRENT_DESIGN
|
||||
}
|
||||
|
||||
sgsIf {$Q_SDC_FILE == ""} {
|
||||
set_property -disable_next_button
|
||||
show_text "<b> You have not selected the SDC file. Please click back and select the SDC file</b>"
|
||||
}
|
||||
sgsIf {$Q_CURRENT_DESIGN == ""} {
|
||||
set_property -disable_next_button
|
||||
show_text "<b> No current design has been specified or selected. Please click back and select the current design </b>"
|
||||
}
|
||||
|
||||
set_property -enable_next_button
|
||||
sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE} >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
} sgsElse {
|
||||
set_property -enable_next_button
|
||||
sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} }
|
||||
set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
}
|
||||
}
|
||||
|
||||
set_header_state "Configure SpyGlass Design Constraint File" complete
|
||||
} sgsElse {
|
||||
set_header_state "Configure SpyGlass Design Constraint File" skipped
|
||||
set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
}
|
||||
|
||||
set_property -step_header "Setup Closure"
|
||||
sgsSet Q_FILE_EXISTS 0
|
||||
get_property system.fileExists $Q_GLOBAL_SGDC -result_variable Q_FILE_EXISTS
|
||||
sgsIf { $Q_FILE_EXISTS == 1 } {
|
||||
set_header_state "Setup Closure" complete
|
||||
show_text "<b> Setup is complete and verified </b>"
|
||||
} sgsElse {
|
||||
set_property -disable_next_button
|
||||
show_text "<b> Setup is incomplete. SGDC file is missing or corrupted. Please Restart or click Back button </b>"
|
||||
}
|
||||
|
||||
@ -1,52 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : sdc_audit
|
||||
// Version: 1.0.1
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
// 1.0.1 19-mar-2014 rule SDC_DataSheet added
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
sdc_audit Constraints Mixed
|
||||
*
|
||||
This goal gives designers the ability to compute Design Coverage and report uncovered objects.
|
||||
*
|
||||
This audit goal gives designers the ability to compute Design Coverage and reports uncovered design objects. The goal will generate a report providing a health card for the SDC, which will include ports and registers that are not constrainted and the reason why constraints are missing on these design objects.
|
||||
|
||||
In addition, the goal is to extract the domain information from SDC Commands. Extracted information is checked for consistency with the SGDC domain information. It informs the user about the conflicting clock domain classifications in SDC. A SGDC file is generated containing all the clock_group information inferred from the SDC constraints, which can be used for further analysis. Generated clocks' corresponding to source clocks are reported in a tabular format.
|
||||
|
||||
|
||||
For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.
|
||||
=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
-mixed
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=constraints
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules SDC_Coverage // Reports how well SDC covers the design
|
||||
|
||||
-rules DomainAnalysis //extract domain infromation from the SDC constraints
|
||||
-rules DomainError //Flags clock domain errors extracted from SDC commands
|
||||
-rules DomainInfo //Generate domain information for interacting clocks from SDC commands
|
||||
-rules Domain_SGDC_Consis //clock_group specified in SGDC not consistent with clock_group extracted from SDC constraints
|
||||
|
||||
-rules SDC_Report01 //Prints table of Generated clocks versus source clocks
|
||||
-rules SDC_DataSheet //VI-85162
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
@ -1,68 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="05/10/10 16:56:35" />
|
||||
<title>sdc_audit</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131431"> </a><h2 class="pHeading1">
|
||||
sdc_audit
|
||||
</h2>
|
||||
<a name="wp1131432"> </a><p class="pBody">
|
||||
This goal gives designers the ability to compute Constraints Coverage and report uncovered objects. Coverage is reported in terms of design objects left uncovered by the specified constraints. Design objects of interest for the rule are ports and registers. An uncovered design object is an indication of missing constraints.
|
||||
</p>
|
||||
<a name="wp1131421"> </a><p class="pBody">
|
||||
The report will identify objects not covered by any constraints and reasons for lack of coverage. If registers are not constrained, run clock_consis goal to get more details. If ports are not constrained, run io_delay goal to get more details.
|
||||
</p>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,108 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : sdc_check
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++
|
||||
sdc_check-mixed
|
||||
*
|
||||
Basic Consistency and Clean Clock Definition
|
||||
*
|
||||
The objective of this step is to detect the inconsistencies in specification of clocks, generated clocks, and perform basic checks on overwritten and conflicting constraints. Without the clean clock definitions, rest of the constraint validation and exception verification would be ineffective. Overwritten and conflicting constraints may not capture the design intent correctly.
|
||||
|
||||
The step also detects the inconsistencies in specification of input/output delays, clock latency, clock uncertainty. Such inconsistencies not only result in synthesis or static timing analysis to produce incorrect results, they can potentially allow these tools to assume a greater slack than available. This translates to insufficient or incomplete optimization by synthesis, which directly affects the QoR.
|
||||
|
||||
Finally this goal checks that all combinational paths are constrained correctly. If a combination path is unconstrained or incorrectly constrained, then tool will perform no timing check on these paths. As a result a device's
|
||||
operation at any specified speed can not be guaranteed.
|
||||
|
||||
For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.
|
||||
=cut+++++++++++
|
||||
|
||||
-mixed
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=constraints
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
-tc_ignore_te=no
|
||||
-ignore_io_if_fp=yes
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
// Check for Clock Issues
|
||||
-rules Const_Struct04a // Overwritten constraint detected
|
||||
-rules Const_Struct05 // Conflicting constraints detected
|
||||
-overloadrules Const_Struct05+severity=Warning
|
||||
-rules Clk_Gen01a // Clock not driven by a clock constraint
|
||||
-overloadrules Clk_Gen01a+severity=Error
|
||||
-rules Clk_Gen01b // Clock driven by a constant value or hanging
|
||||
-rules Clk_Gen02 // Constrained clock not used as a clock
|
||||
-overloadrules Clk_Gen02+severity=Info
|
||||
-rules Clk_Gen03 // A generated clock is not in the fanout of it source clock
|
||||
-overloadrules Clk_Gen03+severity=Error
|
||||
-rules Clk_Gen05 // Some clocks in the same clock domain have a different root clock
|
||||
-rules Clk_Gen06 // Multiple paths exist from the clock pin of a sequential cell to different clock sources
|
||||
-rules Clk_Gen08 // Object on which clock is generated should not be a port
|
||||
-rules Clk_Gen09 // Clock source pin is in the fanout of another clock, but is not generated by that clock
|
||||
-overloadrules Clk_Gen09+severity=Error
|
||||
-rules Clk_Gen22 // set_input_delay/set_output_delay has been specified on a clock port
|
||||
-rules Clk_Gen23 // Incorrectly defined generated clock
|
||||
//-rules Clk_Gen23a //Formal rule for Incorrectly defined Generated clock
|
||||
-overloadrules Clk_Gen23+severity=Error
|
||||
|
||||
-rules SDC_Methodology66 // set_case_analysis applied on a design object conflicts with the propagated value due to other set_case_analysis commands
|
||||
-rules SDC_Methodology67 // set_case_analysis applied on the output of a flop conflicts with the value propagated at its input
|
||||
-rules Clk_Lat08 // set_clock_latency is set to negative value
|
||||
-rules Clk_Uncert01 // Clock_uncertainty constraint set on an object which is not a real or generated clock
|
||||
-rules Clk_Uncert03 // Inter clock uncertainty not defined between synchronous clocks
|
||||
-rules Clk_Uncert06 // set_clock_uncertainty is set to negative value
|
||||
|
||||
// Check for I/O Delay Issues
|
||||
-rules Inp_Del01b // Input not constrained by set_input_delay
|
||||
-overloadrules Inp_Del01b+severity=Error
|
||||
-rules Inp_Del03a // Input constraint associated with wrong (or, incomplete set of) clocks
|
||||
-overloadrules Inp_Del03a+severity=Error
|
||||
-rules Inp_Del08 // set_input_delay is set on the same input relative to multiple clocks but -add_delay missing
|
||||
-overloadrules Inp_Del08+severity=Error
|
||||
-rules Op_Del01b // Output has no set_output_delay constraint
|
||||
-overloadrules Op_Del01b+severity=Error
|
||||
-rules Op_Del03a // Output constraint associated with wrong (or, incomplete set of) clocks
|
||||
-overloadrules Op_Del03a+severity=Error
|
||||
-rules Op_Del08 // set_output_delay is set on the same output relative to multiple clocks but -add_delay is missing
|
||||
-overloadrules Op_Del08+severity=Error
|
||||
-rules Load02a // Load values are outside technology limits
|
||||
-overloadrules Load02a+severity=Error
|
||||
-rules Inp_Trans01a // Input transition or drive or driving cell is not defined for input
|
||||
-overloadrules Inp_Trans01a+severity=Error
|
||||
-rules SDC_Methodology07 // Delay value for constraint set_max_time_borrow is not within the clock period of the clock driving the latch
|
||||
|
||||
// Check for Combinational Path Issues
|
||||
-rules Combo_Paths01 // Combinational port to port path is unconstrained
|
||||
-overloadrules Combo_Paths01+severity=Error
|
||||
-rules Combo_Paths02 // Path specified in sdc file (through set_max_delay/set_min_delay) has max_delay < min_delay
|
||||
-rules Combo_Paths03 // Combinational path has output_delay+input_delay > clock period or output_delay+input_delay > set_max_delay
|
||||
-overloadrules Combo_Paths03+severity=Error
|
||||
-rules Show_Case_Analysis
|
||||
-rules Show_Clock_Propagation
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
<html>
|
||||
<head>
|
||||
<title>sdc_check</title>
|
||||
<h1>SDC Check</h1>
|
||||
</head>
|
||||
<body>
|
||||
<p> The objective of this step is to detect the inconsistencies in specification of clocks, generated clocks, and perform basic checks on overwritten and conflicting constraints. Without the clean clock definitions, rest of the constraint validation and exception verification would be ineffective. Overwritten and conflicting constraints may not capture the design intent correctly.</p>
|
||||
<p>The step also detects the inconsistencies in specification of input/output delays, clock latency, clock uncertainty. Such inconsistencies not only result in synthesis or static timing analysis to produce incorrect results, they can potentially allow these tools to assume a greater slack than available. This translates to insufficient or incomplete optimization by synthesis, which directly affects the QoR.</p>
|
||||
<p>Finally this goal checks that all combinational paths are constrained correctly. If a combination path is unconstrained or incorrectly constrained, then tool will perform no timing check on these paths. As a result a device's
|
||||
operation at any specified speed can not be guaranteed</p>
|
||||
|
||||
<p>To debug issues with this goal, first debug all the SDC Parse violations. Such violations lead to incomplete parsing of the SDC file, and many constraints needed could have been ignored due to Parse errors</p>
|
||||
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,17 +0,0 @@
|
||||
##########################################################################
|
||||
# SpyGlass Constraints Methodology
|
||||
#
|
||||
# Version: 1.0
|
||||
#
|
||||
# Revision History:
|
||||
# Ver Date Comments
|
||||
# 1.0 18-Jun-2008 Initial version
|
||||
#
|
||||
# Copyright Atrenta Inc, 2008. All rights reserved.
|
||||
##########################################################################
|
||||
# This is the setup file for SDC Validation
|
||||
##########################################################################
|
||||
|
||||
set_property -step_header "SDC Checks for Clocks, I/O and Feedthroughs"
|
||||
set_parameters {pt chip clk_gen01_generate_report strict tc_ignore_latch_enable tc_ignore_te ignore_io_if_fp}
|
||||
|
||||
@ -1,41 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : sdc_equiv
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++
|
||||
sdc_equiv-mixed
|
||||
*
|
||||
Constriants Equivalece Checking
|
||||
*
|
||||
The objective of this step is to ensure that versions of constraints file are equivalent for the same design. As design goes through iterations, so does constraints. This steps helps designers to ensure that design intent is preserved on account of such iterations.
|
||||
|
||||
For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.
|
||||
=cut+++++++++++
|
||||
-mixed
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=const_mgmt,constraints
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Equiv_SDC // Check equivalence between two SDCs for the same design
|
||||
-rules Show_Clock_Propagation
|
||||
-rules Show_Case_Analysis
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
@ -1,85 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="05/10/10 16:53:56" />
|
||||
<title>sdc_equiv</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131468"> </a><h2 class="pHeading1">
|
||||
sdc_equiv
|
||||
</h2>
|
||||
<a name="wp1131469"> </a><p class="pBody">
|
||||
The objective of this step is to ensure that versions of constraints file are equivalent for the same design. As design goes through iterations, so does constraints. This steps helps designers to ensure that design intent is preserved on account of such iterations.
|
||||
</p>
|
||||
<a name="wp1131471"> </a><p class="pBody">
|
||||
This debug of this rule is typically iterative. The user would need to resolve equivalence issues in the following order - set_case_analysis, clocks (primary and generated), I/O Delay, Timing Exceptions and other constraints. Unless you fix set_case_analysis issues, you won't see clock related issues. This order is important to prevent noise from being reported in the equivalence. Consider the following example
|
||||
</p>
|
||||
<a name="wp1131473"> </a><h5 class="pHeading5">
|
||||
SDC1
|
||||
</h5>
|
||||
<div class="pPreformatted"><pre class="pPreformatted">
|
||||
create_clock -name c1 -period 10 -source [a/b/clk]<a name="wp1131474"> </a>
|
||||
set_input_delay 10 -clock [c1] [get_ports {in1}]<a name="wp1131475"> </a>
|
||||
</pre></div>
|
||||
<a name="wp1131477"> </a><h5 class="pHeading5">
|
||||
SDC2
|
||||
</h5>
|
||||
<div class="pPreformatted"><pre class="pPreformatted">
|
||||
create_clock -name c2 -period 11 -source [a/b/clk]<a name="wp1131478"> </a>
|
||||
set_input_delay 10 -clock [c2] [get_ports {in1}]<a name="wp1131479"> </a>
|
||||
</pre></div>
|
||||
<a name="wp1131481"> </a><p class="pBody">
|
||||
In this example clocks C1 and C2 are not equivalent. If clocks are not checked before set_input_delay, the equivalence will unnecessarily report the input delays to be not equivalent.
|
||||
</p>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,96 +0,0 @@
|
||||
##########################################################################
|
||||
# SpyGlass Constraints Methodology
|
||||
#
|
||||
# Version: 1.1
|
||||
#
|
||||
# Revision History:
|
||||
# Ver Date Comments
|
||||
# 1.0 18-Jun-2008 Initial version
|
||||
# 1.1 05-Aug-2010 Proper Setup manager for sdc_equiv
|
||||
# Copyright Atrenta Inc, 2008. All rights reserved.
|
||||
##########################################################################
|
||||
# This is the setup file for SDC Validation
|
||||
##########################################################################
|
||||
register_variable Q_ASK_FOR_SGDC 0
|
||||
register_variable Q_ASK_FOR_SDC 0
|
||||
register_variable Q_FLOW_TYPE 0
|
||||
register_variable Q_SDC_FILE_1
|
||||
register_variable Q_SDC_FILE_2
|
||||
register_variable Q_BLOCK_NAME ""
|
||||
register_variable Q_CURRENT_DESIGN ""
|
||||
register_variable Q_GLOBAL_SGDC "$WDIR/constraints.sgdc"
|
||||
|
||||
set_property -show_index
|
||||
set_property -hide_step_numbering
|
||||
#This step will show the help
|
||||
set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/sdc_equivalence_before_you_start.htm
|
||||
set_header_state "Before You Start" complete
|
||||
#In this step we get the type of flow and sdc/sgdc files
|
||||
set_property -step_header "Configure SpyGlass Design Constraint File" -prereq {"Before You Start"}
|
||||
|
||||
create_form -label "CONFIGURE SGDC FILE" {
|
||||
# show_text "If you have a SGDC file already added to the setup, then select no for both the options"
|
||||
get_bool -text "Do you have a SGDC file?" -result_variable Q_ASK_FOR_SGDC -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 }
|
||||
get_bool -text "Do you have a SDC file" -result_variable Q_ASK_FOR_SDC -auto_proceed -style radio -geometry { -side bottom -expand 0 }
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
}
|
||||
set_property -disable_next_button
|
||||
sgsIf { ( $Q_ASK_FOR_SGDC == 1 ) && ( $Q_ASK_FOR_SDC == 1 ) } {
|
||||
show_text "<b>You have to either specify SGDC file(with sdc_data refering to SDC file) or a SDC file which will enable spyglass to automatically create SGDC file for you. Please click back and select one of them. If you select no for both, setup will create a boilerplate SGDC file for you to populate.</b>"
|
||||
}
|
||||
|
||||
sgsIf { $Q_ASK_FOR_SGDC == 1 } {
|
||||
set_property -enable_next_button
|
||||
get_file -type {"SGDC Files" "*.sgdc"} -fileExt { "SGDC Files" "*.sgdc" } -result_variable Q_SGDC_FILE -text "Please select the SGDC file"
|
||||
sgsExec { /bin/cp {get_variable $Q_SGDC_FILE } { get_variable $Q_GLOBAL_SGDC } }
|
||||
set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
} sgsElse {
|
||||
sgsIf {$Q_ASK_FOR_SDC ==1} {
|
||||
set_property -enable_next_button
|
||||
# get_bool -text "Choose Yes if you would like to do block top equivalence, and no if you like to do reference implement equivalence for same top" -buttons {"Yes" "No"} -result_variable Q_FLOW_TYPE -auto_proceed -geometry { -side bottom -expand 0 }
|
||||
|
||||
sgsIf {$Q_FLOW_TYPE == 1} {
|
||||
create_form -label "Configure SDC File" {
|
||||
get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_1 -text "Please select the SDC file(s) for top module"
|
||||
get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_2 -text "Please select the SDC file(s) for block"
|
||||
set_sgdc_curr_design -text "Enter Top Design" -result_variable Q_CURRENT_DESIGN
|
||||
get_string -text "Please enter the block name" -result_variable Q_BLOCK_NAME
|
||||
}
|
||||
sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo block -name {get_variable $Q_BLOCK_NAME} >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_1} -mode flatTop >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_BLOCK_NAME} >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_2} -mode block >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
} sgsElse {
|
||||
create_form -label "Configure SDC File" {
|
||||
get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_1 -text "Please select the reference SDC file(s)"
|
||||
get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_2 -text "Please select the implement SDC file(s)"
|
||||
set_sgdc_curr_design -text "Enter Top Design" -result_variable Q_CURRENT_DESIGN
|
||||
}
|
||||
sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_1} -mode reference >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_2} -mode implement >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
}
|
||||
} sgsElse {
|
||||
|
||||
show_text "Please add a SGDC file or enable previously selected SGDC files"
|
||||
set_constraints
|
||||
}
|
||||
}
|
||||
|
||||
set_header_state "Configure SpyGlass Design Constraint File" complete
|
||||
|
||||
|
||||
set_property -step_header "Set Parameters" -prereq {"Configure SpyGlass Design Constraint File"}
|
||||
set_parameters {equiv_sdc_ambiguous_clock_file equiv_sdc_constraint_file equiv_sdc_tolerance}
|
||||
set_header_state "Set Parameters" complete
|
||||
|
||||
set_property -step_header "Setup Closure" -prereq {"Before You Start" "Configure SpyGlass Design Constraint File"}
|
||||
show_text "Please review the SGDC files created in this setup"
|
||||
set_constraints $Q_GLOBAL_SGDC
|
||||
show_text "Setup is complete and verified"
|
||||
set_header_state "Setup Closure" complete
|
||||
|
||||
@ -1,53 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : sdc_exception_struct
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
// 1.0.1 28-Feb-2014 VI-84582 (SCG01 to SCG05 rules are added to guideware2.0)
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++
|
||||
sdc_exception_struct-mixed
|
||||
*
|
||||
Check Timing Exceptions Structurally
|
||||
*
|
||||
The objective of this step is to check that Timing Exceptions specified in a constraints file as are on paths which are structurally connected. This step is a pre-requisite, before the paths can be verified formally to be correct. Exceptions set on paths that are structurally not connected are redundant and increase the runtime of implementation tools.
|
||||
|
||||
For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.
|
||||
=cut+++++++++++
|
||||
-mixed
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=constraints
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules False_Path01 // False path reference points are not connected
|
||||
-rules False_Path09 // False path uses same clock in its -from and -to lists
|
||||
-rules MCP01 // Multi cycle path reference points are not connected
|
||||
-rules MCP05 // set_multicycle_path setup/hold over or under defined
|
||||
-rules TE_Conflict01 // Overlap between different timing exceptions commands
|
||||
|
||||
-rules Show_Case_Analysis
|
||||
-rules Show_Clock_Propagation
|
||||
|
||||
-rules SCG01 //SCG01 to SCG05 added for VI-84582
|
||||
-rules SCG02
|
||||
-rules SCG03
|
||||
-rules SCG04
|
||||
-rules SCG05
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
@ -1,68 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="05/10/10 16:53:56" />
|
||||
<title>sdc_exception_struct</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131464"> </a><h2 class="pHeading1">
|
||||
sdc_exception_struct
|
||||
</h2>
|
||||
<a name="wp1131465"> </a><p class="pBody">
|
||||
The objective of this step is to check that Timing Exceptions specified in a constraints file are on paths which are structurally connected. This step is a pre-requisite, before the paths can be verified formally to be correct. Exceptions set on paths that are structurally not connected are redundant and indicate the possibility of typos in specifying the exceptions.
|
||||
</p>
|
||||
<a name="wp1131467"> </a><p class="pBody">
|
||||
Before debugging this goal ensure that goal clock_consis has been cleaned. Incomplete/incorrect clock can result in noise to be generated for rules in this goal. The rules in this goal can be debugged in any order. To debug False_Path01 and MCP01, open the incremental schematic and try to traverse from the start point to see where the path is broken or blocked that causes the exceptions not to be structurally connected. If there are violations from TE_Conflict01, remove overlapping exceptions. Even though tools provide a well defined order of precedence when exceptions overlap (False Path > Multi Cycle Path > Max/Min Delay), however that order may not be what the designer intended.
|
||||
</p>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,16 +0,0 @@
|
||||
##########################################################################
|
||||
# SpyGlass Constraints Methodology
|
||||
#
|
||||
# Version: 1.0
|
||||
#
|
||||
# Revision History:
|
||||
# Ver Date Comments
|
||||
# 1.0 18-Jun-2008 Initial version
|
||||
#
|
||||
# Copyright Atrenta Inc, 2008. All rights reserved.
|
||||
##########################################################################
|
||||
# This is the setup file for SDC Validation
|
||||
##########################################################################
|
||||
|
||||
set_property -step_header "Check for Structual Correctness of Exceptions"
|
||||
set_parameters {tc_ignore_clk_to_clk tc_clk_pairs_for_fp strict}
|
||||
@ -1,48 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : sdc_gen
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
Generates Constraints Mixed
|
||||
*
|
||||
This goal gives designers the ability to create SDC templates from RTL or netlist.
|
||||
*
|
||||
This goal gives designers the ability to create SDC templates from RTL or netlist. This requires the users to identify correct clock sources (in the .sgdc file)
|
||||
|
||||
This goal is useful if you have an RTL, but, don't have the associated SDC. The template will help create a bare-bone structure, where, the actual numbers can be filled up later by the user.
|
||||
|
||||
For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.
|
||||
=cut++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
-mixed
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=constraints
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
// The following rules belongs to constraints policy
|
||||
-rules SDC_GenerateIncr // Generate a template constraints file for a block
|
||||
|
||||
//The following rules belong to clock-reset policy and may be needed for debug
|
||||
//-policies=clock-reset
|
||||
//-rules Info_Case_Analysis
|
||||
//-sdc2sgdc
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
@ -1,15 +0,0 @@
|
||||
<html>
|
||||
<head>
|
||||
<title>sdc_gen</title>
|
||||
<h1>SDC Generation</h1>
|
||||
</head>
|
||||
<body>
|
||||
|
||||
<p>This goal gives designers the ability to create SDC templates from RTL or netlist. This requires the users to identify correct clock sources (in the .sgdc file)</p>
|
||||
|
||||
<p>This goal is useful if you have an RTL, but, don't have the associated SDC. The template will help create a bare-bone structure, where, the actual numbers can be filled up later by the user.</p>
|
||||
|
||||
<p>For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.</p>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,234 +0,0 @@
|
||||
##########################################################################
|
||||
# SpyGlass Constraints Methodology
|
||||
#
|
||||
# Version: 1.4
|
||||
#
|
||||
# Revision History:
|
||||
# Ver Date Comments
|
||||
# 1.0 18-Jun-2008 Initial version
|
||||
# 1.1 28-Jul-2008 1) Fixed incorrect documentation in setup
|
||||
# (29544, 31450)
|
||||
# 2) Fixed redundancy in steps (31170)
|
||||
# 3) Enhanced to edit gensdcConstraintsfile.txt (31468)
|
||||
# 1.2 15-Dec-2008 1) New CDC Setup Manager integrated
|
||||
# 2) Console Setup improved
|
||||
# 1.3 24-Dec-2008 1) register output file issues fixed in Console
|
||||
# 2) Added comments
|
||||
# 1.4 20-Jan-2009 1) Fixed VIs 36448, 35958
|
||||
# Copyright Atrenta Inc, 2008. All rights reserved.
|
||||
##########################################################################
|
||||
# This is the SGS script to setup Constraints Generation
|
||||
##########################################################################
|
||||
##########################################################################
|
||||
# Register Variables to be used in the script here
|
||||
##########################################################################
|
||||
# Variable to check if clock has been saved in SGDC
|
||||
register_variable Q_SGDC_MOD 0
|
||||
# Variable to check if clock setup has been run once
|
||||
register_variable Q_RUN_ONCE 0
|
||||
# Variable to check if user wants to run clock setup
|
||||
register_variable Q_RUN_CLK_SETUP 0
|
||||
# Variable to check if file exists
|
||||
register_variable Q_FILE_EXISTS 0
|
||||
# Variable to check, if user has SGDC that he wants to user instead of clock setup
|
||||
register_variable Q_ASK_FOR_SGDC 0
|
||||
# Variable to check, if user want parametrized SDC
|
||||
register_variable Q_ASK_FOR_PARAM 0
|
||||
# Variable to check, SDC Generation has been run once. This way when user hits back button
|
||||
# and comes back to the step again, it will load the exisiting run
|
||||
register_variable Q_SDC_GEN_ONCE 0
|
||||
# Variable to check, SDC Generation has been run once incrementall. This way when user hits back button
|
||||
# and comes back to the step again, it will load the exisiting run
|
||||
register_variable Q_SDC_GEN_INCR 0
|
||||
# Variable to store whether last run was with Param or not
|
||||
register_variable Q_LAST_RUN_WITH_PARAM 0
|
||||
|
||||
source $SPYGLASS_HOME/auxi/common_setup/init_central.sgs
|
||||
|
||||
##########################################################################
|
||||
# Common Procedures
|
||||
##########################################################################
|
||||
## Before you start
|
||||
set_property -show_index
|
||||
set_property -hide_step_numbering
|
||||
|
||||
register_variable USE_DESIGN_CLOCKS 1
|
||||
register_variable USE_BBOX_RESOLUTION 1
|
||||
source $SPYGLASS_HOME/auxi/common_setup/get_central_status.sgs
|
||||
|
||||
set_property -step_header "Before You Start" -show_index
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Constraints_Generation_Setup.htm
|
||||
set_header_state "Before You Start" complete
|
||||
## Resolve Blackboxes
|
||||
source $SPYGLASS_HOME/auxi/common_setup/bb_resolution/bb_resolution.sgs
|
||||
##########################################################################
|
||||
# Setup Step 1 ...................
|
||||
# Identify all clocks using CDC Setup
|
||||
##########################################################################
|
||||
|
||||
source $SPYGLASS_HOME/.Methodology/Clock-reset/CDC-Setup-Manager/CDC_Setup_Manager_clock_setup.sgs
|
||||
|
||||
# Add generated SGDC file to the project with recommended constraint as clocks
|
||||
set_constraints $PRJFILES_DIR/cdc_setup_clocks.sgdc -constraints {clock} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Copy_and_Modify_autoclocks.sgdc.htm -label "Identified Clocks"
|
||||
|
||||
# set_header_state "Review Clocks" complete
|
||||
#} sgsElse {
|
||||
## User would have reached this when he created SGDC file and hence Review of Clock Setup Wizard setup is skipped
|
||||
# set_header_state "Review Clocks" skipped
|
||||
#}
|
||||
|
||||
##########################################################################
|
||||
# Setup Step 2 ...................
|
||||
# Use the SGDC file and generate all clocks in SDC format
|
||||
##########################################################################
|
||||
|
||||
set_property -step_header "Choose Constraints" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" }
|
||||
|
||||
# Copy the default gensdcConstraintsFile.txt from installation and let the user edit it
|
||||
#sgsExec { /bin/cp $SPYGLASS_HOME/policies/constraints/gensdcConstraintsFile.txt $WDIR/gensdcConstraintsFile.txt }
|
||||
sgsCopyFile -file $SPYGLASS_HOME/policies/constraints/gensdcConstraintsFile.txt -target $WDIR/gensdcConstraintsFile.txt
|
||||
edit_file $WDIR/gensdcConstraintsFile.txt -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Generating_Clocks.htm
|
||||
|
||||
set_header_state "Choose Constraints" complete
|
||||
|
||||
# Now Run the Generation. Ask the user if he/she wants parameterized SDC
|
||||
set_property -step_header "Generate SDC file" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" "Choose Constraints"}
|
||||
set_sgdc_state -enable {get_variable $SETUP_CLOCKS_SGDC}
|
||||
create_form -label "ASK_FOR_PARAMETRIZATION" {
|
||||
get_bool -text "Do you create parametrizable SDC? (Default is No)" -result_variable Q_ASK_FOR_PARAM -button {"Yes" "No"} -auto_proceed -geometry { -side bottom }
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Generate_SDC_Template.htm
|
||||
}
|
||||
sgsIf { $Q_SDC_GEN_ONCE == 0 || $Q_ASK_FOR_PARAM != $Q_LAST_RUN_WITH_PARAM } {
|
||||
sgsSet Q_SDC_GEN_ONCE 1
|
||||
sgsIf { $Q_ASK_FOR_PARAM == 0} {
|
||||
sgsSet Q_LAST_RUN_WITH_PARAM 0
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -auto_run -must_run -text "Running Goal Gen_Constraints to generate the chosen constraints." -auto_proceed
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -text "Running Goal Gen_Constraints to generate the chosen constraints."
|
||||
} sgsElse {
|
||||
sgsSet Q_LAST_RUN_WITH_PARAM 1
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt -tc_enable_param_sdc_flow='yes'" -auto_run -must_run -text "Running Goal Gen_Constraints to generate the chosen constraints." -auto_proceed
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt" -text "Running Goal Gen_Constraints to generate the chosen constraints."
|
||||
}
|
||||
} sgsElse {
|
||||
sgsIf { $Q_ASK_FOR_PARAM == 0} {
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -text "Running Goal Gen_Constraints to generate the chosen constraints."
|
||||
} sgsElse {
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt -tc_enable_param_sdc_flow='yes'" -text "Running Goal Gen_Constraints to generate the chosen constraints."
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
set_header_state "Generate SDC file" complete
|
||||
##########################################################################
|
||||
# Setup Step 3 ...................
|
||||
# Use the seed file from Step 2 to add generate more constraints
|
||||
# This step is same as step2, except that SGDC input is different
|
||||
##########################################################################
|
||||
set_property -step_header "Choose More Constraints" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" "Choose Constraints" "Generate SDC file"}
|
||||
|
||||
# Set the constraints, so that user can now setup the seed file for a future run
|
||||
#set_constraints -constraints {"sdc_data"} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Adding_Constraints_Incrementally.htm
|
||||
# Copy the file generated in the last run, into the run directory so that user can specify the seed, without any
|
||||
# references to the path
|
||||
#sgsExec { /bin/cp $WDIR/spyglass_reports/constraints/*.sdc $PRJFILES_DIR/ }
|
||||
#
|
||||
register_variable ALL_OLD_FILE_LIST
|
||||
get_property console.SGDClist -result_variable ALL_OLD_FILE_LIST
|
||||
set_sgdc_state -disable { get_variable $ALL_OLD_FILE_LIST }
|
||||
|
||||
register_variable Q_SDC_INCR_FILE
|
||||
register_variable Q_CURRENT_DESIGN
|
||||
create_form -label "CONFIGURE SDC FILE" {
|
||||
get_file -type { "SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_INCR_FILE -text "Please select the SDC file generated from the gen_sdc run along with seed sdc file"
|
||||
set_sgdc_curr_design -text "Enter Current Design" -result_variable Q_CURRENT_DESIGN
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Adding_Constraints_Incrementally.htm
|
||||
}
|
||||
sgsIf {$Q_SDC_INCR_FILE == ""} {
|
||||
set_property -disable_next_button
|
||||
show_text "<b> You have not selected the SDC file. Please click back and select the SDC file</b>"
|
||||
}
|
||||
sgsIf {$Q_CURRENT_DESIGN == ""} {
|
||||
set_property -disable_next_button
|
||||
show_text "<b> No current design has been specified or selected. Please click back and select the current design </b>"
|
||||
}
|
||||
set_property -enable_next_button
|
||||
register_variable Q_INCREMENTAL_SGDC "$PRJFILES_DIR/incr.sgdc"
|
||||
sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_INCREMENTAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_INCREMENTAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_INCR_FILE} -mode seed >> {get_variable $Q_INCREMENTAL_SGDC} }
|
||||
set_constraints $Q_INCREMENTAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
|
||||
# Edit the side file constaining constraints to be generated
|
||||
edit_file $WDIR/gensdcConstraintsFile.txt -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Choose_Constraints_to_be_added_incrementally.htm
|
||||
|
||||
set_header_state "Choose More Constraints" complete
|
||||
|
||||
set_property -step_header "Generate SDC incrementally" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" "Choose Constraints" "Generate SDC file" "Choose More Constraints"}
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Populate_SDC_Template.htm
|
||||
# Now Run the Generation again. Based on what user chose last time, the option to generate parametrized SDC will be
|
||||
# jsut inherited from the last run
|
||||
sgsIf { $Q_SDC_GEN_INCR == 0 || $Q_ASK_FOR_PARAM != $Q_LAST_RUN_WITH_PARAM } {
|
||||
sgsSet Q_SDC_GEN_INCR 1
|
||||
sgsIf { $Q_ASK_FOR_PARAM == 0} {
|
||||
sgsSet Q_LAST_RUN_WITH_PARAM 0
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -must_run -auto_run -text "Running Goal Gen_Constraints to generate the chosen constraints."
|
||||
} sgsElse {
|
||||
sgsSet Q_LAST_RUN_WITH_PARAM 1
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt -tc_enable_param_sdc_flow='yes'" -must_run -auto_run -text "Running Goal Gen_Constraints to generate the chosen constraints."
|
||||
}
|
||||
} sgsElse {
|
||||
sgsIf { $Q_ASK_FOR_PARAM == 0} {
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt" -text "Running Goal Gen_Constraints to generate the chosen constraints."
|
||||
} sgsElse {
|
||||
run_setup_template $SPYGLASS_HOME/.Methodology/Constraints/rtl/gen_sdc -additionalCmd "-gen_sdc_constraints_file=$WDIR/gensdcConstraintsFile.txt -gen_sdc_param_file=$SPYGLASS_HOME/policies/constraints/gensdcParamSdc.txt -tc_enable_param_sdc_flow='yes'" -text "Running Goal Gen_Constraints to generate the chosen constraints."
|
||||
}
|
||||
}
|
||||
|
||||
register_variable Q_FINAL_SGDC "$PRJFILES_DIR/final.sgdc"
|
||||
register_variable Q_FINAL_SGDC_EXISTS 0
|
||||
register_variable Q_LAST_SETUP 0
|
||||
get_property console.SGDClist -result_variable ALL_OLD_FILE_LIST
|
||||
set_sgdc_state -disable { get_variable $ALL_OLD_FILE_LIST }
|
||||
|
||||
get_property system.fileExists { get_variable $Q_FINAL_SGDC } -result_variable Q_FINAL_SGDC_EXISTS
|
||||
## Here we ask the user to again create an SGDC file from last runs generated files. This will be the final SGDC file which will be used during actual goal run
|
||||
|
||||
sgsIf { $Q_FINAL_SGDC_EXISTS == 1 } {
|
||||
create_form -label "CONFIGURE LAST SETUP" {
|
||||
get_bool -text "Final SGDC File already exists, do you want to re-use it?" -result_variable Q_LAST_SETUP -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 }
|
||||
}
|
||||
}
|
||||
|
||||
sgsIf {$Q_LAST_SETUP == 0} {
|
||||
create_form -label "CONFIGURE SDC FILE" {
|
||||
get_file -type { "SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_INCR_FILE -text "Please select the SDC file generated from the gen_sdc run along with seed sdc file"
|
||||
set_sgdc_curr_design -text "Enter Current Design" -result_variable Q_CURRENT_DESIGN
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Adding_Constraints_Incrementally.htm
|
||||
}
|
||||
sgsIf {$Q_SDC_INCR_FILE == ""} {
|
||||
set_property -disable_next_button
|
||||
show_text "<b> You have not selected the SDC file. Please click back and select the SDC file</b>"
|
||||
}
|
||||
sgsIf {$Q_CURRENT_DESIGN == ""} {
|
||||
set_property -disable_next_button
|
||||
show_text "<b> No current design has been specified or selected. Please click back and select the current design </b>"
|
||||
}
|
||||
set_property -enable_next_button
|
||||
|
||||
sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_FINAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_FINAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_INCR_FILE} -mode seed >> {get_variable $Q_FINAL_SGDC} }
|
||||
}
|
||||
#sgsExec { /bin/cp $WDIR/spyglass_reports/constraints/*.sdc $PRJFILES_DIR/ }
|
||||
set_header_state "Generate SDC incrementally" complete
|
||||
|
||||
set_property -step_header "Setup Closure" -hide_label -show_index -enable_next_button -set_prereq_steps {"Before You Start" "Design Clocks" "Choose Constraints" "Generate SDC file" "Choose More Constraints" "Generate SDC incrementally" }
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/gen_sdc_setup_closure.htm
|
||||
set_constraints $Q_FINAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
|
||||
set_header_state "Setup Closure" complete
|
||||
|
||||
@ -1,42 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : sdc_hier_equiv
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++
|
||||
sdc_hier_equiv-mixed
|
||||
*
|
||||
Hierarchical Constriants Checking
|
||||
*
|
||||
The objective of this step is to ensure that constraints are consistent across block hierarchies. This step will help you to check consistency of Block level constraint with sub-chip/chip level constraints for clocks, I/O delays. E.g. a block may have been synthesized with a lower frequency clock (bigger clock period), but at chip level is being driven by a higher frequency clock (smaller clock period). The block may not function correctly.
|
||||
|
||||
For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.
|
||||
=cut+++++++++++
|
||||
-mixed
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=constraints,const_mgmt
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules IO_Consis04 // Sum of input delay and output delay should not exceed clock period
|
||||
-rules Equiv_SDC_Block // Check Equivalence between Top and Block level SDC
|
||||
-rules Show_Case_Analysis
|
||||
-rules Show_Clock_Propagation
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
@ -1,85 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="05/10/10 16:53:56" />
|
||||
<title>sdc_hier_equiv</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131482"> </a><h2 class="pHeading1">
|
||||
sdc_hier_equiv
|
||||
</h2>
|
||||
<a name="wp1131483"> </a><p class="pBody">
|
||||
The objective of this step is to ensure that constraints are consistent across block hierarchies. This step will help you to check consistency of Block level constraint with sub-chip/chip level constraints for clocks, I/O delays. E.g. a block may have been synthesized with a lower frequency clock (bigger clock period), but at chip level is being driven by a higher frequency clock (smaller clock period). The block may not function correctly.
|
||||
</p>
|
||||
<a name="wp1131485"> </a><p class="pBody">
|
||||
This debug of this rule is typically iterative. The user would need to resolve equivalence issues in the following order - set_case_analysis, clocks (primary and generated), I/O Delay, Timing Exceptions and other constraints. Unless you fix set_case_analysis issues, you won't see clock related issues. This order is important to prevent noise from being reported in the equivalence. Consider the following example
|
||||
</p>
|
||||
<a name="wp1131487"> </a><h5 class="pHeading5">
|
||||
SDC1 at Top
|
||||
</h5>
|
||||
<div class="pPreformatted"><pre class="pPreformatted">
|
||||
create_clock -name c1 -period 10 -source [clk]<a name="wp1131488"> </a>
|
||||
set_input_delay 10 -clock [c1] [get_ports {in1}]<a name="wp1131489"> </a>
|
||||
</pre></div>
|
||||
<a name="wp1131491"> </a><h5 class="pHeading5">
|
||||
SDC2 at Block
|
||||
</h5>
|
||||
<div class="pPreformatted"><pre class="pPreformatted">
|
||||
create_clock -name c1 -period 11 -source [block/clk]<a name="wp1131492"> </a>
|
||||
set_input_delay 10 -clock [c1] [get_ports {block/in1}]<a name="wp1131493"> </a>
|
||||
</pre></div>
|
||||
<a name="wp1131495"> </a><p class="pBody">
|
||||
In this example clocks C1 (in top) and C1 (in block) are not equivalent. If clocks are not checked before set_input_delay, the equivalence will unnecessarily report the input delays to be not equivalent.
|
||||
</p>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,96 +0,0 @@
|
||||
##########################################################################
|
||||
# SpyGlass Constraints Methodology
|
||||
#
|
||||
# Version: 1.1
|
||||
#
|
||||
# Revision History:
|
||||
# Ver Date Comments
|
||||
# 1.0 18-Jun-2008 Initial version
|
||||
# 1.1 05-Aug-2010 Proper Setup manager for sdc_equiv
|
||||
# Copyright Atrenta Inc, 2008. All rights reserved.
|
||||
##########################################################################
|
||||
# This is the setup file for SDC Validation
|
||||
##########################################################################
|
||||
register_variable Q_ASK_FOR_SGDC 0
|
||||
register_variable Q_ASK_FOR_SDC 0
|
||||
register_variable Q_FLOW_TYPE 1
|
||||
register_variable Q_SDC_FILE_1
|
||||
register_variable Q_SDC_FILE_2
|
||||
register_variable Q_BLOCK_NAME ""
|
||||
register_variable Q_CURRENT_DESIGN ""
|
||||
register_variable Q_GLOBAL_SGDC "$WDIR/constraints.sgdc"
|
||||
|
||||
set_property -show_index
|
||||
set_property -hide_step_numbering
|
||||
#This step will show the help
|
||||
set_property -step_header "Before You Start" -show_progress_bar -hide_quality_bar
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/hierarchical_check_before_you_start.htm
|
||||
set_header_state "Before You Start" complete
|
||||
#In this step we get the type of flow and sdc/sgdc files
|
||||
set_property -step_header "Configure SpyGlass Design Constraint File" -prereq {"Before You Start"}
|
||||
|
||||
create_form -label "CONFIGURE SGDC FILE" {
|
||||
# show_text "If you have a SGDC file already added to the setup, then select no for both the options"
|
||||
get_bool -text "Do you have a SGDC file?" -result_variable Q_ASK_FOR_SGDC -buttons {"Yes" "No"} -auto_proceed -style radio -geometry { -side bottom -expand 0 }
|
||||
get_bool -text "Do you have a SDC file" -result_variable Q_ASK_FOR_SDC -auto_proceed -style radio -geometry { -side bottom -expand 0 }
|
||||
show_html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
}
|
||||
set_property -disable_next_button
|
||||
sgsIf { ( $Q_ASK_FOR_SGDC == 1 ) && ( $Q_ASK_FOR_SDC == 1 ) } {
|
||||
show_text "<b>You have to either specify SGDC file(with sdc_data refering to SDC file) or a SDC file which will enable spyglass to automatically create SGDC file for you. Please click back and select one of them. If you select no for both, setup will create a boilerplate SGDC file for you to populate.</b>"
|
||||
}
|
||||
|
||||
sgsIf { $Q_ASK_FOR_SGDC == 1 } {
|
||||
set_property -enable_next_button
|
||||
get_file -type {"SGDC Files" "*.sgdc"} -fileExt { "SGDC Files" "*.sgdc" } -result_variable Q_SGDC_FILE -text "Please select the SGDC file"
|
||||
sgsExec { /bin/cp {get_variable $Q_SGDC_FILE } { get_variable $Q_GLOBAL_SGDC } }
|
||||
set_constraints $Q_GLOBAL_SGDC -constraints {current_design sdc_data} -html $SPYGLASS_HOME/.Methodology/Constraints/doc/Configure_SpyGlass_Design_Constraint_File.htm
|
||||
} sgsElse {
|
||||
sgsIf {$Q_ASK_FOR_SDC ==1} {
|
||||
set_property -enable_next_button
|
||||
# get_bool -text "Choose Yes if you would like to do block top equivalence, and no if you like to do reference implement equivalence for same top" -buttons {"Yes" "No"} -result_variable Q_FLOW_TYPE -auto_proceed -geometry { -side bottom -expand 0 }
|
||||
|
||||
sgsIf {$Q_FLOW_TYPE == 1} {
|
||||
create_form -label "Configure SDC File" {
|
||||
get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_1 -text "Please select the SDC file(s) for top module"
|
||||
get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_2 -text "Please select the SDC file(s) for block"
|
||||
set_sgdc_curr_design -text "Enter Top Design" -result_variable Q_CURRENT_DESIGN
|
||||
get_string -text "Please enter the block name" -result_variable Q_BLOCK_NAME
|
||||
}
|
||||
sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_1} -mode flatTop >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo block -name {get_variable $Q_BLOCK_NAME} >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_BLOCK_NAME} >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_2} -mode block >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
} sgsElse {
|
||||
create_form -label "Configure SDC File" {
|
||||
get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_1 -text "Please select the reference SDC file(s)"
|
||||
get_file -type {"SDC Files" "*.sdc" } -fileExt { "SDC Files" "*.sdc" } -allow_multiple -result_variable Q_SDC_FILE_2 -text "Please select the implement SDC file(s)"
|
||||
set_sgdc_curr_design -text "Enter Top Design" -result_variable Q_CURRENT_DESIGN
|
||||
}
|
||||
sgsExec { /bin/cp $SPYGLASS_HOME/.Methodology/Constraints/setup_template/constraints.sgdc {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo current_design {get_variable $Q_CURRENT_DESIGN} > {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_1} -mode reference >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
sgsExec { echo sdc_data -file {get_variable $Q_SDC_FILE_2} -mode implement >> {get_variable $Q_GLOBAL_SGDC} }
|
||||
}
|
||||
} sgsElse {
|
||||
|
||||
show_text "Please add a SGDC file or enable previously selected SGDC files"
|
||||
set_constraints
|
||||
}
|
||||
}
|
||||
|
||||
set_header_state "Configure SpyGlass Design Constraint File" complete
|
||||
|
||||
|
||||
set_property -step_header "Set Parameters" -prereq {"Configure SpyGlass Design Constraint File"}
|
||||
set_parameters {equiv_sdc_ambiguous_clock_file equiv_sdc_constraint_file equiv_sdc_tolerance}
|
||||
set_header_state "Set Parameters" complete
|
||||
|
||||
set_property -step_header "Setup Closure" -prereq {"Before You Start" "Configure SpyGlass Design Constraint File"}
|
||||
show_text "Please review the SGDC files created in this setup"
|
||||
set_constraints $Q_GLOBAL_SGDC
|
||||
show_text "Setup is complete and verified"
|
||||
set_header_state "Setup Closure" complete
|
||||
|
||||
@ -1,63 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : sdc_redundancy
|
||||
// Version: 1.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++
|
||||
sdc_redundancy-mixed
|
||||
*
|
||||
Check for Redundancy in Constraints
|
||||
*
|
||||
The objective of this step is to remove any redundancy in the constraints and perform checks that might facilitate better retargeting. This is an optional step and solely the discretion of the design group.
|
||||
|
||||
For more details about this goal, please refer to the SpyGlass-Constraints-Methodology.pdf file in the doc subdirectory of your SpyGlass installation.
|
||||
=cut+++++++++++
|
||||
-mixed
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=constraints
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules High_Fan03 // High fanout net identified
|
||||
|
||||
-rules False_Path04a // False path specification excludes a large number of paths
|
||||
|
||||
-rules MCP04a // Multicycle path specification covers a large number of paths
|
||||
|
||||
-rules Disable_Timing02 // Clock path blocked by set_disable_timing
|
||||
|
||||
-rules SDC_Report01 // Prints table of generated clocks versus source clocks
|
||||
|
||||
-rules Clk_Gen21 // set_propagated_clock set on a virtual clock
|
||||
-rules Clk_Uncert07 // No crossing exists between clocks for which inter-clock uncertainty is defined
|
||||
-rules Clk_Trans16 // set_clock_transition set on virtual clocks
|
||||
|
||||
-rules False_Path03 // Unnecessary use of through in false-path
|
||||
-rules MCP03 // Unnecessary use of through in multi-cycle path
|
||||
|
||||
-rules Inp_Del07a // Input constraints are incorrect relative to a range of clock period
|
||||
-rules Op_Del07a // Output constraints are incorrect relative to a range of clock period
|
||||
-rules Inp_Del09 // Not all pins on the same bus have the same input delay
|
||||
-rules Op_Del09 // Not all pins on the same bus have the same output delay
|
||||
|
||||
-rules Show_Case_Analysis
|
||||
-rules Show_Clock_Propagation
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
@ -1,71 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="05/10/10 16:53:56" />
|
||||
<title>sdc_redundancy</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131511"> </a><h2 class="pHeading1">
|
||||
sdc_redundancy
|
||||
</h2>
|
||||
<a name="wp1131512"> </a><p class="pBody">
|
||||
The objective of this step is to remove any redundancy in the constraints and perform checks that might facilitate better retargeting.
|
||||
</p>
|
||||
<a name="wp1131514"> </a><p class="pBody">
|
||||
Before debugging this goal ensure that goals clock_consis, io_delay, combo_path, and structural_exception have been cleaned.
|
||||
</p>
|
||||
<a name="wp1131516"> </a><p class="pBody">
|
||||
This is an optional step and solely the discretion of the design group. Rules can be debugged in no particular order. Rule debug is similar to the other goals described in the Methodology.
|
||||
</p>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,16 +0,0 @@
|
||||
##########################################################################
|
||||
# SpyGlass Constraints Methodology
|
||||
#
|
||||
# Version: 1.0
|
||||
#
|
||||
# Revision History:
|
||||
# Ver Date Comments
|
||||
# 1.0 18-Jun-2008 Initial version
|
||||
#
|
||||
# Copyright Atrenta Inc, 2008. All rights reserved.
|
||||
##########################################################################
|
||||
# This is the setup file for SDC Validation
|
||||
##########################################################################
|
||||
|
||||
set_property -step_header "Check for Constraints Redundant Constraints"
|
||||
set_parameters {clk_gen01_generate_report ignore_io_if_fp inp_percent_max inp_percent_min op_percent_max op_percent_min num_falsepath_max num_mcpath_max tc_ignore_latch_enable tc_ignore_te}
|
||||
@ -1,8 +0,0 @@
|
||||
The need for DFT-optimized design:
|
||||
|
||||
Manufacturing test is performed by patterns automatically
|
||||
generated by ATPG (automatic test pattern generation) tools.
|
||||
To operate effectively, these tools require that the circuits
|
||||
be correctly designed for testing.
|
||||
|
||||
This and subsequent steps directly address this issue.
|
||||
@ -1,57 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare Goal File
|
||||
//
|
||||
// Goal Name : dft_abstract
|
||||
// Version : 5.3.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
// Added: Short description of rules and parameters
|
||||
// 5.3.0 20-Jun-2014 Guidware 2.0 Content Consistency
|
||||
//
|
||||
// Copyright Synopsys Inc, 2019. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
dft_abstract
|
||||
*
|
||||
Generate abstract view of the design.
|
||||
*
|
||||
This goal includes rules which will create the abstract view of design:
|
||||
|
||||
For more details about this goal, please refer to the
|
||||
SpyGlass-DFT-Methodology.pdf file in the doc subdirectory of your
|
||||
SpyGlass installation
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=dft
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
-block_abstract // Enables abstraction setup rules
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
-dftTreatBBoxAsScanwrapped=on // Treat all black-boxes as scan-wrapped
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Soc_00 // This rule creates abstract view of current design
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,69 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="01/24/13 15:43:42" />
|
||||
<title>dft_abstract</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1132474"> </a><h2 class="pHeading1">
|
||||
dft_abstract
|
||||
</h2>
|
||||
<div class="pSmartList1"><ul class="pSmartList1">
|
||||
<a name="wp1132475"> </a><div class="pSmartList1"><li>The goal helps in creating an Abstract Model for a Block.</li></div>
|
||||
<a name="wp1132493"> </a><div class="pSmartList1"><li>SpyGlass DFT supports a hierarchical SoC methodology in which a simplified abstract model of the block can be created when rule checking the block. The model can then be used in lieu of the original RTL for efficient rule checking at the top/SoC level.</li></div>
|
||||
<a name="wp1132496"> </a><div class="pSmartList1"><li>The creation of the abstract model is done by running the <em style="font-weight: bold" class="cEmphasis">dft_abstract</em> goal on the block. </li></div>
|
||||
<a name="wp1132499"> </a><div class="pSmartList1"><li>When using abstract models for one or more lower level blocks in a design, the <em style="font-weight: bold" class="cEmphasis">dft_abstract_validate</em> goal verifies that the constraints under which the abstraction was done are met in the current design.</li></div>
|
||||
<a name="wp1132532"> </a><div class="pSmartList1"><li>The use of the hierarchical SoC methodology for DFT is described in greater detail in the SpyGlass SoC Methodology User Guide.</li></div>
|
||||
</ul></div>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
|
Before Width: | Height: | Size: 19 KiB |
@ -1,200 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare Goal File
|
||||
//
|
||||
// Goal Name : dft_best_practice
|
||||
// Version : 5.5.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 5.5.0 11-Jun-2015 Initial version
|
||||
// Added: Coverage_audit
|
||||
// Added: Info_coverage
|
||||
// Added: Async_07
|
||||
// Added: Async_08
|
||||
// Added: Clock_11
|
||||
// Added: Clock_11_capture
|
||||
// Added: Clock_26
|
||||
// Added: Scan_22
|
||||
// Added: Scan_24
|
||||
// Added: Scan_25
|
||||
// Added: Scan_26
|
||||
// Added: Soc_04
|
||||
// Added: TA_09
|
||||
// Added: Diagnose_testclock
|
||||
// Added: Diagnose_testmode
|
||||
// Added: Info_forcedScan
|
||||
// Added: Info_inferredNoScan
|
||||
// Added: Info_noScan
|
||||
// Added: Info_scanchain
|
||||
// Added: Info_scanwrap
|
||||
// Added: Info_testmode_conflict_01
|
||||
// Added: Info_uncontrollable
|
||||
// Added: Info_undetectCause
|
||||
// Added: Info_unobservable
|
||||
// Added: Info_untestable
|
||||
//
|
||||
// Copyright Synopsys Inc, 2019. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
dft_best_practice
|
||||
*
|
||||
Check the design for best practices to find issues that may
|
||||
decrease ATPG effectiveness
|
||||
*
|
||||
ATPG tools typically cannot effectively handle structures such
|
||||
as asynchronous combinatorial loops, testclock also being used
|
||||
as data, tristate enables that are not one-hot encoded, flops
|
||||
having large fanin cones, large timing paths, etc. Due to these
|
||||
structures, often, there is negative impact on the ATPG tools
|
||||
in terms of runtime or inadequate coverage achievement.
|
||||
|
||||
Similarly, latches should be made transparent when the capture
|
||||
mode conditions are simulated with testclocks at their
|
||||
"return to" state.
|
||||
|
||||
Designers can avoid these pitfalls by discovering such structural
|
||||
issues at the RTL coding stage. Designers may use this template
|
||||
to check their designs for best practrices even without testmode
|
||||
setup knowledge.
|
||||
|
||||
For more details about this goal, please refer to the
|
||||
SpyGlass-DFT-Methodology.pdf file in the doc subdirectory of your
|
||||
SpyGlass installation
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=dft
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Coverage_audit // Analyze coverage for circuit
|
||||
|
||||
-rules Info_coverage // Estimate fault and test coverage
|
||||
|
||||
-rules Async_02_capture // FF set or reset fanin cone must not contain ffs, latches or bboxes in capture mode
|
||||
|
||||
-rules Async_03 // Verifies that all async pins can go to their inactive state at the same time
|
||||
|
||||
-rules Async_07 // Asynchronous set/reset sources should be inactive during shift mode
|
||||
-overloadrules Async_07+msgLabel=Async_07_M1+severity=Error
|
||||
|
||||
-rules Async_08 // Asynchronous set/reset pins of all the flops should be fully controllable during capture.
|
||||
|
||||
-rules Async_11 // Avoid using set/reset signal as data signal in capture mode
|
||||
|
||||
-rules BIST_01 // Restrict input cone width for BIST (with appropriate -flopInFaninCount=<value>)
|
||||
|
||||
-rules Clock_04 // Do not use clock signals as data signals
|
||||
|
||||
-rules Clock_08 // No merging of test clocks
|
||||
|
||||
-rules Clock_09 // No logic in common with clock and data
|
||||
|
||||
-rules Clock_11 // All clock sources must be testclock controlled in shift mode
|
||||
-overloadrules Clock_11+msgLabel=Clock_11_M1+severity=Error
|
||||
|
||||
-rules Clock_11_capture // All clock sources must be testclock controlled in capture mode
|
||||
|
||||
-rules Clock_16 // Capture FFs must not have any data paths from FFs capturing on opposite edge of the same clock
|
||||
|
||||
-rules Clock_17 // Capture clocks must not be gated by flip-flops capturing on the same clock
|
||||
|
||||
-rules Clock_21 // Clocks must not drive flip-flop set or reset pins
|
||||
|
||||
-rules Clock_26 // Testclock constraint must not be applied on sensitized fanout of another test clock in Shift or Capture mode
|
||||
|
||||
-rules Clock_27 // Detects edge inconsistency between CGC and driven flip-flops
|
||||
|
||||
-rules Clock_28 // No combinational reconvergence to flip-flops clock pins
|
||||
|
||||
-rules Latch_02 // No combinational loops from transparent latches
|
||||
|
||||
-rules Latch_08 // Latches should be transparent in capture mode
|
||||
-overloadrules Latch_08+msgLabel=Latch_08_WRN_01+severity=Error
|
||||
|
||||
-rules Latch_10 // All latch enables must be combinationally derived from root level inputs
|
||||
|
||||
-rules Scan_07 // No registered (sequentially derived) or combinationally derived internal test_mode signals
|
||||
|
||||
-rules Scan_22 // Scan chains must have lockup latches at domain crossing
|
||||
|
||||
-rules Scan_24 // All flip-flops should be part of some scan chain
|
||||
|
||||
-rules Scan_25 // Scan chains must not contain invertors in scan path
|
||||
|
||||
-rules Scan_26 // Scan chains must contain lockup latch at chain end
|
||||
|
||||
-rules Soc_04 // Show design state for a given tag
|
||||
|
||||
-rules TA_09 // Suggests test points to improve controllability and observability
|
||||
|
||||
-rules Topology_01 // Combinational loops are not allowed
|
||||
|
||||
-rules Topology_02 // No asynchronous port to port paths
|
||||
|
||||
-rules Topology_03 // Avoid sequentially derived asynchronous signals with common clock
|
||||
|
||||
-rules Topology_05 // Wire-OR and Wire-AND are not allowed
|
||||
|
||||
-rules Topology_10 // Avoid long logic paths (with appropriate -pathDepth=<value>)
|
||||
|
||||
-rules Topology_13 // No combinational reconvergence to flip-flops asynchronous pins
|
||||
|
||||
-rules Tristate_06 // Tristate bus enables must be fully decoded so that exactly one driver is active at any time
|
||||
|
||||
-rules Tristate_07_shift // All Inout ports are inputs only in shift mode
|
||||
|
||||
-rules Diagnose_testclock // Display instances that blocks testclock propagation
|
||||
|
||||
-rules Diagnose_testmode // Display instances that blocks testmode propagation
|
||||
|
||||
-rules Info_forcedScan // Displays all registers and flip-flops specified as 'scan'
|
||||
|
||||
-rules Info_inferredNoScan // Displays all flip-flops which have been inferred as no_scan
|
||||
|
||||
-rules Info_noFault // Reports all the instances which are specified as no fault or inferred as no fault
|
||||
|
||||
-rules Info_noScan // Displays all registers and flip-flops specified as 'no_scan'
|
||||
|
||||
-rules Info_scanchain // Displays all properly stitched scanchains
|
||||
|
||||
-rules Info_scanwrap // Report scanwrap related information
|
||||
|
||||
-rules Info_synthRedundant // Display pins that are likely to be absent in an optimized netlist
|
||||
|
||||
-rules Info_testclock // Display test clock propagation
|
||||
|
||||
-rules Info_testmode // Display testmode simulation results
|
||||
|
||||
-rules Info_testmode_conflict_01 // Display conflict in user specified testmode with respect to simulation result of fanin cone
|
||||
|
||||
-rules Info_uncontrollable // Shows nets with imperfect controllability
|
||||
|
||||
-rules Info_undetectCause // Display undetectable fault information
|
||||
|
||||
-rules Info_unobservable // Shows all unobservable pins
|
||||
|
||||
-rules Info_untestable // Display untestable faults caused by test mode
|
||||
|
||||
-rules Info_unused // Display faults having no effect on system function
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,79 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="01/24/13 15:43:42" />
|
||||
<title>dft_best_practice</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1132572"> </a><h2 class="pHeading1">
|
||||
dft_best_practice
|
||||
</h2>
|
||||
<a name="wp1132573"> </a><p class="pBody">
|
||||
Review the violation messages, have better understanding about the issue by bringing up the schematic if appropriate and fix the design issue. Note the fix for these issues may be very design-specific.
|
||||
</p>
|
||||
<a name="wp1132575"> </a><h2 class="pHeading2">
|
||||
Make Latches Transparent (One of the objectives of this goal)
|
||||
</h2>
|
||||
<div class="pSmartList1"><ul class="pSmartList1">
|
||||
<a name="wp1132576"> </a><div class="pSmartList1"><li>Latch_08 violations (see the description of Latch_08 in the SpyGlass DFT User Guide section on Latch Rules) detect latches that are not transparent in capture mode. Non-transparent latches can be diagnosed with Info_testmode for capture. </li></div>
|
||||
<a name="wp1132603"> </a><div class="pSmartList1"><li>Select a Latch_08 violation and display in the IS. </li></div>
|
||||
<a name="wp1132606"> </a><div class="pSmartList1"><li>If the latch enable has a non-X but an inactive value then either a test_mode constraint should have the complementary value, or some device in the fan-in to this latch enable should produce the complementary value.</li></div>
|
||||
<a name="wp1132609"> </a><div class="pSmartList1"><li>If the latch enable has no value, then either the logic feeding this enable should be modified so that the enable is forced active during capture or new test_mode constraints must be defined.</li></div>
|
||||
<a name="wp1132624"> </a><p class="pBodyRelative">
|
||||
<br />
|
||||
<img src="dft_best_practice-01.jpg" height="138" width="625" id="wp1132617" border="0" hspace="0" vspace="0"/><br />
|
||||
|
||||
</p>
|
||||
</ul></div>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,39 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare Goal File
|
||||
//
|
||||
// dft_bist_ready
|
||||
// Version: 5.4.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 5.4.0 12-Nov-2014 Version as in 5.4.0
|
||||
//
|
||||
// Copyright Synopsys Inc, 2019. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
dft_bist_ready
|
||||
*
|
||||
Make design amicable to bist and test-compression
|
||||
*
|
||||
This "bist ready" step provides value not only for designs with Logic BIST
|
||||
(Built-In-Self-Test) but also for designs with ATPG Compression, as the rules
|
||||
report on various forms of X-propagation which is detrimental to both.
|
||||
|
||||
This "bist ready" step is designed to ensure that design is aligned with
|
||||
bist and test-compression requirements. SpyGlass DFT does not do the bist or
|
||||
compression insertion but rather deals with X-propagation and large fanin cone.
|
||||
|
||||
For more details about this goal, please refer to the
|
||||
SpyGlass-DFT-Methodology.pdf file in the doc subdirectory of your
|
||||
SpyGlass installation
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
-policies=dft
|
||||
-rules BIST_01
|
||||
-rules BIST_02
|
||||
-rules BIST_03
|
||||
-rules BIST_04
|
||||
-rules BIST_05
|
||||
|
||||
-rules Info_testmode
|
||||
-rules Info_testclock
|
||||
@ -1,151 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare Goal File
|
||||
//
|
||||
// Goal Name : dft_dsm_best_practice
|
||||
// Version : 5.5.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 5.5.0 11-Jun-2015 Initial version
|
||||
// Added: Atspeed_07
|
||||
// Added: Atspeed_11 (and moved to top)
|
||||
// Added: Atspeed_14
|
||||
// Added: Atspeed_22
|
||||
// Added: Atspeed_30
|
||||
// Added: CG_01_shift
|
||||
// Added: CG_01_capture
|
||||
// Added: CG_01_atspeed
|
||||
// Added: CG_02_capture
|
||||
// Added: CG_02_atspeed
|
||||
// Added: CG_03_capture
|
||||
// Added: CG_03_atspeed
|
||||
// Added: CG_07
|
||||
// Added: CG_generateReport
|
||||
//
|
||||
// Copyright Synopsys Inc, 2019. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
dft_dsm_best_practice
|
||||
*
|
||||
High stuck at coverage is a necessary but not sufficient
|
||||
condition to achieving high transition coverage. This
|
||||
template contains rules that address the special needs of
|
||||
such topics as d-pin controllability, test clock domains
|
||||
and path issues.
|
||||
*
|
||||
DFT for stuck at testing involved a scan and a low speed
|
||||
capture clock. The purpose of scan was to create a state
|
||||
that both exercised and observed specific faults.
|
||||
Transition testing requires two vectors and two clocks
|
||||
fired at system speed. The first clock pulse causes a
|
||||
state transition which imposes additional DFT requirements
|
||||
beyond stuck at DFT. The second clock pulse must be from
|
||||
the same clock source as the first pulse which also imposes
|
||||
special DFT considerations.
|
||||
|
||||
Since transition tests are performed with high speed clocks,
|
||||
false paths and multicycle paths must be taken into account
|
||||
since various faults along such paths cannot be transition
|
||||
tested.
|
||||
|
||||
This template contains rules that address these issues,
|
||||
rules that help diagnose transition rule violations.
|
||||
|
||||
For more details about this goal, please refer to the
|
||||
SpyGlass-DFT-DSM-Methodology.pdf file in the doc
|
||||
subdirectory of your SpyGlass installation
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=dft_dsm,dft
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Info_transitionCoverage_audit // Analyze transition coverage for circuit
|
||||
|
||||
-rules Info_transitionCoverage // Evaluate transition coverage for design
|
||||
|
||||
-rules Atspeed_11 // All clock sources must be controlled by an atspeed clock
|
||||
-overloadrules Atspeed_11+severity=Error
|
||||
|
||||
-rules Atspeed_03 // Async logic in the functional mode should not interact synchronously in the capture at-speed mode
|
||||
|
||||
-rules Atspeed_04 // Synchronously interacting logic in the functional mode should not be clocked by asynchronous clocks in the capture at-speed mod
|
||||
|
||||
-rules Atspeed_05 // All false paths or multicycle paths in the functional mode should be blocked in the capture at-speed mode
|
||||
|
||||
-rules Atspeed_06 // All paths crossing asynchronous clock domains should be blocked
|
||||
|
||||
-rules Atspeed_07 // Clock gating for each domain in the capture at-speed mode should be done using a separate signal
|
||||
|
||||
-rules Atspeed_09 // Data pin of scan flip-flop must be fully controllable
|
||||
|
||||
-rules Atspeed_14 // Test clocks must not be used as data signals
|
||||
|
||||
-rules Atspeed_19 // Latches should be transparent in capture/captureatspeed mode or when testclocks/atspeed clocks are off
|
||||
|
||||
-rules Atspeed_20 // Asynchronous set/reset pins of all the flops should be fully controllable during capture atspeed mode
|
||||
|
||||
-rules Atspeed_22 // No merging of atspeed clocks in capture atspeed mode
|
||||
|
||||
-rules Atspeed_25 // No combinational reconvergence to flip-flops asynchronous pins
|
||||
|
||||
-rules Atspeed_30 // No combinational reconvergence to flip-flops clock pins
|
||||
|
||||
-rules CG_01_shift // Clock gating cell enables should be enabled in shift mode
|
||||
-overloadrules CG_01_shift+severity=Error
|
||||
|
||||
-rules CG_01_capture // Clock gating cell enables should be controllable to on state in capture mode
|
||||
-overloadrules CG_01_capture+severity=Error
|
||||
|
||||
-rules CG_01_atspeed // Clock gating cell enables should be controllable to on state in atspeed mode
|
||||
-overloadrules CG_01_atspeed+severity=Error
|
||||
|
||||
-rules CG_02_capture // CGC enables should be controllable to off state in capture mode
|
||||
|
||||
-rules CG_02_atspeed // CGC enables should be controllable to off state in atspeed mode
|
||||
|
||||
-rules CG_03_capture // System enable pins on clock gating cell should be observable in capture mode
|
||||
|
||||
-rules CG_03_atspeed // System enable pins on clock gating cell should be observable in atspeed mode
|
||||
|
||||
-rules CG_07 // Detects edge inconsistency between CGC and driven flip-flops
|
||||
|
||||
-rules CG_generateReport // Generate a text report with details of all clock gating cells in design
|
||||
|
||||
-rules Diagnose_02 // At-speed paths must not be blocked by testmode signals
|
||||
|
||||
-rules Diagnose_03 // Faults blocked by false paths or multi-cycle paths
|
||||
|
||||
-rules Diagnose_04 // Faults in paths crossing clock domains cannot be tested
|
||||
|
||||
-rules Info_atSpeedClock // Displays at-speed test clock propagation
|
||||
|
||||
-rules Info_noAtspeed // Displays all registers and flip-flops specified as 'no_atspeed'
|
||||
|
||||
-rules Info_synthRedundant // Display pins that are likely to be absent in an optimized netlist
|
||||
|
||||
-rules Info_testclock // Display test clock propagation
|
||||
|
||||
-rules Info_testmode // Display testmode simulation results
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,204 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="01/24/13 15:43:42" />
|
||||
<title>dft_dsm_best_practice</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
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<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
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<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
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<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1132978"> </a><h2 class="pHeading1">
|
||||
dft_dsm_best_practice
|
||||
</h2>
|
||||
<div class="pSmartList1"><ul class="pSmartList1">
|
||||
<a name="wp1132979"> </a><div class="pSmartList1"><li>Select an Atspeed_09 violation in IS.</li></div>
|
||||
<div class="pSmartList2"><ul class="pSmartList2">
|
||||
<a name="wp1132980"> </a><div class="pSmartList2"><li>If the cause is a combinational loop, then review in the schematic viewer if a test_mode is missing or has been improperly declared. Otherwise, the design may have to be modified to allow use of a test_mode to break the loop.</li></div>
|
||||
<a name="wp1132988"> </a><div class="pSmartList2"><li>If the case is a multiple driven net/floating net, review if a test_mode is missing or has been improperly declared. </li></div>
|
||||
<a name="wp1132991"> </a><div class="pSmartList2"><li>If the case is a black box, then create a scan wrapper for the<br />module.</li></div>
|
||||
<a name="wp1132994"> </a><div class="pSmartList2"><li>If the case is a non-lockup/Non-transparent latch, then review if a test_mode is missing or has been improperly declared.</li></div>
|
||||
<a name="wp1132997"> </a><div class="pSmartList2"><li>If the case is a non-scan flip-flop then reconsider the reasons for this to not be scannable. Create a "scan" constraint for this flip-flop to determine the coverage impact.</li></div>
|
||||
<a name="wp1133000"> </a><div class="pSmartList2"><li>If the case is a constant value net has been reached, then review if a test_mode is missing or has been improperly declared.</li></div>
|
||||
</ul></div>
|
||||
<a name="wp1133003"> </a><div class="pSmartList1"><li>Select an Atspeed_19 violation in the IS. Display the enable fan-in cone back to primary inputs to see if or how this logic should be enabled in captureATspeed mode.</li></div>
|
||||
<a name="wp1133009"> </a><div class="pSmartList1"><li>Select an Atspeed_03 violation in the IS. Display the clock fan-in cone back to primary inputs for both flip-flops. If the root level system clocks that feed these flip-flops are synchronous, then add -domain <xx> to each of the clock constraints. If the clocks are not synchronous, then redesign the switching logic or the test_mode constraints so that the clocks are not combined in captureATspeed mode.</li></div>
|
||||
<a name="wp1133012"> </a><div class="pSmartList1"><li>Select an Atspeed_04 violation in the IS. Display the clock fan-in cone back to primary inputs for both flip-flops. If the root level clocks that feed these flip-flops are declared asynchronous but shouldn't be, then remove or change -domain <xx> to each of the clock constraints so the clocks are in different domains. If the clocks are synchronous, then redesign the switching logic so that the clocks are combined in captureATspeed mode.</li></div>
|
||||
<a name="wp1133015"> </a><div class="pSmartList1"><li>Diagnose_04 can be used to display faults that cannot be tested but use caution since numbers of faults may be involved.</li></div>
|
||||
<a name="wp1133018"> </a><div class="pSmartList1"><li>Select an Atspeed_05 violation in IS mode to see paths that declared as multi-cycle or false-path in the SDC file or in SGDC file. If any path should be considered for transition testing, then remove that path from the constraint file.</li></div>
|
||||
<a name="wp1133021"> </a><div class="pSmartList1"><li>Select an Atspeed_06 violation in IS mode to see paths that cross clock domains.</li></div>
|
||||
<div class="pSmartList2"><ul class="pSmartList2">
|
||||
<a name="wp1132909"> </a><div class="pSmartList2"><li>If the domains should be considered as synchronous, then add domain <xx> to the atspeed clocks</li></div>
|
||||
<a name="wp1133027"> </a><div class="pSmartList2"><li>If the domains are asynchronous, then consider blocking the path with a design change.</li></div>
|
||||
</ul></div>
|
||||
<a name="wp1132911"> </a><div class="pSmartList1"><li>Diagnose_03 may be used to view faults that are involved in false path or multi-cycle paths.</li></div>
|
||||
</ul></div>
|
||||
<a name="wp1132913"> </a><h2 class="pHeading2">
|
||||
Estimate Coverage
|
||||
</h2>
|
||||
<div class="pSmartList1"><ul class="pSmartList1">
|
||||
<a name="wp1132914"> </a><div class="pSmartList1"><li>Info_transitionCoverage may be used to estimate the transition fault coverage if ATPG were run based on the current circuit and SGDC constraints.</li></div>
|
||||
<a name="wp1133041"> </a><div class="pSmartList1"><li>If the coverage estimate reported falls below expectation, run Info_transitionCoverage_audit to find the major causes of low atspeed test (transition delay) coverage.</li></div>
|
||||
</ul></div>
|
||||
<a name="wp1132916"> </a><h2 class="pHeading2">
|
||||
Improve Coverage
|
||||
</h2>
|
||||
<a name="wp1132917"> </a><p class="pBody">
|
||||
Info_transitionCoverage_audit issues a report of the major causes of low atspeed test (transition delay) coverage. The rule is not intended to diagnose these causes. Instead, the at-speed rules corresponding to a particular cause should be used for diagnosis.
|
||||
</p>
|
||||
<a name="wp1132919"> </a><h5 class="pHeading5">
|
||||
Method
|
||||
</h5>
|
||||
<a name="wp1132920"> </a><p class="pBody">
|
||||
For each cause, the rule will find the cause and list the coverage that would be obtained if that cause were fixed. After the incremental coverage improvement for each cause is computed, the new total coverage is listed. This total coverage will be an increasing value that approaches 100%.
|
||||
</p>
|
||||
<a name="wp1132922"> </a><p class="pBody">
|
||||
The following categories are the primary reason for coverage data not reaching 100%:
|
||||
</p>
|
||||
<div class="pSmartList1"><ul class="pSmartList1">
|
||||
<a name="wp1132923"> </a><div class="pSmartList1"><li>Non scan flip-flops</li></div>
|
||||
<a name="wp1132924"> </a><p class="pBodyRelative">
|
||||
Assume all flip-flops are scannable. Force all flip-flops, except flip-flops declared with no_scan constraint, to be considered scannable.
|
||||
</p>
|
||||
<table id="SummaryNotReq1" border="0" cellspacing="0" cellpadding="0" onClick="WWHShowALinksPopup();">
|
||||
<tr>
|
||||
<td height="2" colspan="4" bgcolor="#FFFFFF"></td>
|
||||
<td width="2" height="2" background="images/seertup.gif"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="2" height="2" bgcolor="#FFFFFF"></td>
|
||||
<td height="2" colspan="3" bgcolor="#EEEEEE"></td>
|
||||
<td width="2" height="2" background="images/seeright.gif"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="2" bgcolor="#FFFFFF"></td>
|
||||
<td width="2" bgcolor="#EEEEEE"></td>
|
||||
<td bgcolor="#EEEEEE"><a name="wp1132925"> </a><div class="pNoteRelative">NOTE: Flip-flops that are declared as no_scan, will not be forced scannable.</div></td>
|
||||
<td width="2" bgcolor="#EEEEEE"></td>
|
||||
<td width="2" background="images/seeright.gif"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="2" height="2" bgcolor="#FFFFFF"></td>
|
||||
<td height="2" colspan="3" bgcolor="#EEEEEE"></td>
|
||||
<td width="2" height="2" background="images/seeright.gif"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="2" height="2" background="images/seelflow.gif"></td>
|
||||
<td height="2" colspan="3" background="images/seebttm.gif"></td>
|
||||
<td width="2" height="2" background="images/seertlow.gif"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<table id="SummaryNotReq2" border="0" cellspacing="0" cellpadding="0" onClick="WWHShowALinksPopup();">
|
||||
<tr>
|
||||
<td height="2" colspan="4" bgcolor="#FFFFFF"></td>
|
||||
<td width="2" height="2" background="images/seertup.gif"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="2" height="2" bgcolor="#FFFFFF"></td>
|
||||
<td height="2" colspan="3" bgcolor="#EEEEEE"></td>
|
||||
<td width="2" height="2" background="images/seeright.gif"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="2" bgcolor="#FFFFFF"></td>
|
||||
<td width="2" bgcolor="#EEEEEE"></td>
|
||||
<td bgcolor="#EEEEEE"><a name="wp1133064"> </a><div class="pNoteRelative">NOTE: Flip-flops that are inferred as no_scan, will be forced as scannable.</div></td>
|
||||
<td width="2" bgcolor="#EEEEEE"></td>
|
||||
<td width="2" background="images/seeright.gif"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="2" height="2" bgcolor="#FFFFFF"></td>
|
||||
<td height="2" colspan="3" bgcolor="#EEEEEE"></td>
|
||||
<td width="2" height="2" background="images/seeright.gif"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td width="2" height="2" background="images/seelflow.gif"></td>
|
||||
<td height="2" colspan="3" background="images/seebttm.gif"></td>
|
||||
<td width="2" height="2" background="images/seertlow.gif"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="wp1132927"> </a><div class="pSmartList1"><li>At speed domains of scan flip-flops</li></div>
|
||||
<a name="wp1132928"> </a><p class="pBodyRelative">
|
||||
Assume all scannable flip-flops are at-speed clocked. Force all scannable flip-flops that are not clocked by an -atspeed testclock, to be launch points for transition testing.
|
||||
</p>
|
||||
<a name="wp1132929"> </a><div class="pSmartList1"><li>Uncontrollable data of scan flip-flops</li></div>
|
||||
<a name="wp1132930"> </a><p class="pBodyRelative">
|
||||
Assume the d-pins of scannable flip-flops are fully controllable.
|
||||
</p>
|
||||
<a name="wp1132931"> </a><div class="pSmartList1"><li>Feedback flip-flops</li></div>
|
||||
<a name="wp1132932"> </a><p class="pBodyRelative">
|
||||
Assume all scannable q to d Feedback flip-flops can launch both transitions.
|
||||
</p>
|
||||
<a name="wp1132933"> </a><div class="pSmartList1"><li>Combinational reconvergence</li></div>
|
||||
<a name="wp1132934"> </a><p class="pBodyRelative">
|
||||
Assume all combinational reconvergences are broken.
|
||||
</p>
|
||||
<a name="wp1132935"> </a><div class="pSmartList1"><li>Uncontrollable logic due to hanging terminals</li></div>
|
||||
<a name="wp1132936"> </a><p class="pBodyRelative">
|
||||
Assume all hanging terminals are fully controllable.
|
||||
</p>
|
||||
<a name="wp1132937"> </a><div class="pSmartList1"><li>Tristate enable used for capture</li></div>
|
||||
<a name="wp1132938"> </a><p class="pBodyRelative">
|
||||
Assume enable pin of tristate as a capture node for all domains.
|
||||
</p>
|
||||
<a name="wp1132939"> </a><div class="pSmartList1"><li>Untestable faults on SCANENABLE/SET/RESET</li></div>
|
||||
<a name="wp1132940"> </a><p class="pBodyRelative">
|
||||
Assume both transitions can be detected on SE/SET/RESET control logics.
|
||||
</p>
|
||||
<a name="wp1132941"> </a><div class="pSmartList1"><li>PI and PO used for launch and capture</li></div>
|
||||
<a name="wp1132942"> </a><p class="pBodyRelative">
|
||||
Assume PIs and POs are used for Launch and Capture nodes, respectively.
|
||||
</p>
|
||||
<a name="wp1132943"> </a><div class="pSmartList1"><li>Clock domain crossing</li></div>
|
||||
<a name="wp1132944"> </a><p class="pBodyRelative">
|
||||
Assume all scannable flip-flops are in the same domain.
|
||||
</p>
|
||||
</ul></div>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
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|
||||
// Clear related topics
|
||||
//
|
||||
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|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq3" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
@ -1,58 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare Goal File
|
||||
//
|
||||
// Goal Name : dft_dsm_random_resistance
|
||||
// Version : 5.5.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 5.5.0 11-Jun-2015 Initial version
|
||||
//
|
||||
// Copyright Synopsys Inc, 2019. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
dft_dsm_random_resistance
|
||||
*
|
||||
Reduce the random resistance of the design
|
||||
*
|
||||
For both stuck-at and transition faults, the presence of hard to detect
|
||||
faults has a substantial impact on overall ATPG performance. The ability
|
||||
to measure the density of hard to detect faults in a design early at the
|
||||
RTL stage is valuable. It gives the opportunity to make design changes
|
||||
to address the issue, and enables to quickly measure the impact of the
|
||||
changes. One of the best predictors of the presence of hard to detect
|
||||
faults is the random resistance of a design. This template contains
|
||||
rules that address the special needs of such topics
|
||||
|
||||
For more details about this goal, please refer to the
|
||||
SpyGlass-DFT-DSM-Methodology.pdf file in the doc
|
||||
subdirectory of your SpyGlass installation
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=dft_dsm,dft
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Info_random_resistance // Does the random resistive analysis for the circuit
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
|
Before Width: | Height: | Size: 71 KiB |
|
Before Width: | Height: | Size: 69 KiB |
|
Before Width: | Height: | Size: 26 KiB |
|
Before Width: | Height: | Size: 78 KiB |
|
Before Width: | Height: | Size: 52 KiB |
|
Before Width: | Height: | Size: 48 KiB |
@ -1,101 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare Goal File
|
||||
//
|
||||
// Goal Name : dft_scan_ready
|
||||
// Version : 5.5.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 5.5.0 11-Jun-2015 Initial version
|
||||
// Added : Clock_26
|
||||
// Added : Info_testmode_conflict_01
|
||||
// Added : Info_untestable
|
||||
// Removed: Info_path
|
||||
//
|
||||
// Copyright Synopsys Inc, 2019. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
dft_scan_ready
|
||||
*
|
||||
Make registers scannable
|
||||
*
|
||||
SpyGlass DFT may be run on RTL designs without any built-in test logic or
|
||||
on designs with test mode controls and test clocks. In the first case,
|
||||
SpyGlass will identify the system logic that does not comply with DFT
|
||||
requirements. In the second case, SpyGlass DFT will verify that the
|
||||
design-for-test logic is performing correctly as well as identify where
|
||||
additional design-for-test logic may be required or useful.
|
||||
|
||||
This "scan ready" step is designed to ensure that as many registers in
|
||||
the RTL as possible can easily be replaced with scan equivalents either
|
||||
during logic synthesis or in a post-synthesis step. SpyGlass DFT does
|
||||
not do the scan insertion or scan chain stitching but rather deals with
|
||||
the clocks and the asynchronous signals to ensure compliance with
|
||||
scan replacement requirements.
|
||||
|
||||
For more details about this goal, please refer to the
|
||||
SpyGlass-DFT-Methodology.pdf file in the doc subdirectory of your
|
||||
SpyGlass installation
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policies=dft
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Coverage_audit // Analyze coverage for circuit
|
||||
|
||||
-rules Info_coverage // Estimate fault and test coverage
|
||||
|
||||
-rules Async_07 // Asynchronous set/reset sources should be inactive during shift mode
|
||||
-overloadrules Async_07+msgLabel=Async_07_M1+severity=Error
|
||||
|
||||
-rules Async_08 // Asynchronous set/reset pins of all the flops should be fully controllable during capture.
|
||||
|
||||
-rules Clock_11 // All clock sources must be testclock controlled in shift mode
|
||||
-overloadrules Clock_11+msgLabel=Clock_11_M1+severity=Error
|
||||
|
||||
-rules Clock_11_capture // All clock sources must be testclock controlled in capture mode
|
||||
|
||||
-rules Clock_26 // Testclock constraint must not be applied on sensitized fanout of another test clock in Shift or Capture mode
|
||||
|
||||
-rules Diagnose_testclock // Display instances that blocks testclock propagation
|
||||
|
||||
-rules Diagnose_testmode // Display instances that blocks testmode propagation
|
||||
|
||||
-rules Info_forcedScan // Displays all registers and flip-flops specified as 'scan'
|
||||
|
||||
-rules Info_inferredNoScan // Displays all flip-flops which have been inferred as no_scan
|
||||
|
||||
-rules Info_noScan // Displays all registers and flip-flops specified as 'no_scan'
|
||||
|
||||
-rules Info_scanwrap // Report scanwrap related information
|
||||
|
||||
-rules Info_testclock // Display test clock propagation
|
||||
|
||||
-rules Info_testmode // Display testmode simulation results
|
||||
|
||||
-rules Info_testmode_conflict_01 // Display conflict in user specified testmode with respect to simulation result of fanin cone
|
||||
|
||||
-rules Info_untestable // Display untestable faults caused by test mode
|
||||
|
||||
//------------------------------------------------
|
||||
// End of Rule Registration
|
||||
//------------------------------------------------
|
||||
@ -1,151 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="01/24/13 15:43:42" />
|
||||
<title>dft_scan_ready</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1133589"> </a><h2 class="pHeading1">
|
||||
dft_scan_ready
|
||||
</h2>
|
||||
<div class="pSmartList1"><ul class="pSmartList1">
|
||||
<a name="wp1133590"> </a><div class="pSmartList1"><li>Run the dft_scan_ready goal. </li></div>
|
||||
<a name="wp1133591"> </a><div class="pSmartList1"><li>A flip-flop is considered as scannable if during scanshift:</li></div>
|
||||
<div class="pSmartList2"><ul class="pSmartList2">
|
||||
<a name="wp1133592"> </a><div class="pSmartList2"><li>Its clock can be controlled by a testclock (checked by DFT rule Clock_11) and</li></div>
|
||||
<a name="wp1133593"> </a><div class="pSmartList2"><li>Its set and reset pins (if any) are forced inactive (checked by DFT rule Async_07)</li></div>
|
||||
</ul></div>
|
||||
<a name="wp1133594"> </a><div class="pSmartList1"><li>These two rules may be violated either because test logic has not yet been designed in or because the constraint file has missing or incorrect entries. If there are violations of either rule, then diagnostic rules Diagnose_testclock and Diagnose_testmode can be used to diagnose the cause.</li></div>
|
||||
<a name="wp1133595"> </a><div class="pSmartList1"><li>Any non-scannable flip-flop will reduce the coverage for logic that only feeds that flip-flop as well as logic that is only driven by that flip-flop.</li></div>
|
||||
<a name="wp1133596"> </a><div class="pSmartList1"><li>The dft_scan_ready goal also checks that testmode signals that only control asynchronous set or reset pins should be unrestricted during capture. (checked by DFT rule Async_08)</li></div>
|
||||
<div class="pSmartList2"><ul class="pSmartList2">
|
||||
<a name="wp1133597"> </a><div class="pSmartList2"><li>Restricting such a dedicated signal would result in the set/reset nets not being tested thoroughly.</li></div>
|
||||
<a name="wp1133598"> </a><div class="pSmartList2"><li>Such a violation can be fixed by adding the -scanshift argument to the test_mode constraint to indicate that the constraint only applies during shifting and is a don't care otherwise.</li></div>
|
||||
</ul></div>
|
||||
</ul></div>
|
||||
<a name="wp1133619"> </a><h2 class="pHeading2">
|
||||
Clock_11 Debug
|
||||
</h2>
|
||||
<a name="wp1133620"> </a><p class="pBody">
|
||||
Clock_11 violations detect clock sources (see the description of Clock_11 in the SpyGlass DFT User Guide section on Clock Rules) that are not controlled by test clocks. Each violation indicates the number of flip-flops clocked by this source. Selecting any violation will highlight the source on the schematic. Following is an example shown in the Incremental Schematic.
|
||||
</p>
|
||||
<a name="wp1132945"> </a><p class="pBodyRelative">
|
||||
</p>
|
||||
<div align="left"><img src="dft_scan_ready-08.jpg" height="294" width="625" id="wp1133627" border="0" hspace="0" vspace="0"/></div><p class="pBodyRelative">
|
||||
|
||||
</p>
|
||||
<a name="wp1133643"> </a><p class="pBody">
|
||||
The testclock propagation through the 'Show Case Analysis' mechanism appears automatically in the schematic.
|
||||
</p>
|
||||
<a name="wp1133645"> </a><p class="pBody">
|
||||
You will realize that the testclock propagation stops somewhere in the design:
|
||||
</p>
|
||||
<a name="wp1132761"> </a><p class="pBodyRelative">
|
||||
</p>
|
||||
<div align="left"><img src="dft_scan_ready-09.jpg" height="280" width="625" id="wp1133649" border="0" hspace="0" vspace="0"/></div><p class="pBodyRelative">
|
||||
|
||||
</p>
|
||||
<a name="wp1133661"> </a><p class="pBody">
|
||||
In this example it is clear that the other input of the AND gate should be held at '1' to enable the clock to pass through. The designer applies a 'test_mode' constraint to rectify the situation.
|
||||
</p>
|
||||
<a name="wp1133662"> </a><h2 class="pHeading2">
|
||||
Async_07 Debug
|
||||
</h2>
|
||||
<a name="wp1133663"> </a><p class="pBody">
|
||||
Async_07 violations detect async sources (see the description of Async_07 in the SpyGlass DFT User Guide section on Asynchronous Rules) that are not rendered inactive during scanshift.
|
||||
</p>
|
||||
<div class="pSmartList1"><ul class="pSmartList1">
|
||||
<a name="wp1133664"> </a><div class="pSmartList1"><li>Select a violation and display in the MS.</li></div>
|
||||
<a name="wp1133665"> </a><div class="pSmartList1"><li>The testmode value propagation appears automatically on the schematic.</li></div>
|
||||
<a name="wp1133666"> </a><div class="pSmartList1"><li>Visually find out the root cause why the async source of the flip-flops is held at 'X' or at the active value. This will lead to the conclusion about how possibly a test_mode constraint can be applied to rectify the Async_07 violation.</li></div>
|
||||
</ul></div>
|
||||
<a name="wp1133668"> </a><p class="pBody">
|
||||
In the example below, the schematic shows no constraint was applied on the rst input pin of the design:
|
||||
</p>
|
||||
<a name="wp1133690"> </a><p class="pBodyRelative">
|
||||
</p>
|
||||
<div align="left"><img src="dft_scan_ready-10.jpg" height="233" width="625" id="wp1133691" border="0" hspace="0" vspace="0"/></div><p class="pBodyRelative">
|
||||
|
||||
</p>
|
||||
<a name="wp1133703"> </a><h2 class="pHeading2">
|
||||
Viewing the estimate of fault coverage of the design
|
||||
</h2>
|
||||
<a name="wp1133704"> </a><p class="pBody">
|
||||
The rule Info_coverage estimates the fault/test coverage of the design. The generated reports help in understanding the test health of the design. The following fault browser helps understand the relative testability scores achieved in the design.
|
||||
</p>
|
||||
<a name="wp1132692"> </a><p class="pBodyRelative">
|
||||
</p>
|
||||
<div align="left"><img src="dft_scan_ready-11.jpg" height="256" width="625" id="wp1133711" border="0" hspace="0" vspace="0"/></div><p class="pBodyRelative">
|
||||
|
||||
</p>
|
||||
<a name="wp1132694"> </a><p class="pBody">
|
||||
The following summary reported generated at this stage helps understand the fault status.
|
||||
</p>
|
||||
<a name="wp1133730"> </a><p class="pBodyRelative">
|
||||
</p>
|
||||
<div align="left"><img src="dft_scan_ready-12.jpg" height="259" width="625" id="wp1133731" border="0" hspace="0" vspace="0"/></div><p class="pBodyRelative">
|
||||
|
||||
</p>
|
||||
<a name="wp1133743"> </a><p class="pBody">
|
||||
One may also, optionally, generate a detailed fault report, similar to ATPG, as follows. This report generation is under the control of a switch. Enable this by specifying the following parameter:
|
||||
</p>
|
||||
<a name="wp1133744"> </a><p class="pBody">
|
||||
set_parameter dftGenerateStuckAtFaultReport all
|
||||
</p>
|
||||
<a name="wp1132696"> </a><p class="pBodyRelative">
|
||||
</p>
|
||||
<div align="left"><img src="dft_scan_ready-13.jpg" height="225" width="625" id="wp1133755" border="0" hspace="0" vspace="0"/></div><p class="pBodyRelative">
|
||||
|
||||
</p>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,5 +0,0 @@
|
||||
set_property -step_header "Testclocks for scan"
|
||||
set_constraints -constraints {clock test_mode} -html $SPYGLASS_HOME/.Methodology/DFT/doc/DFT3121.htm
|
||||
#####
|
||||
set_property -step_header "Asynchronous sets and resets for scan"
|
||||
set_constraints -constraints {test_mode} -html $SPYGLASS_HOME/.Methodology/DFT/doc/DFT3122.htm
|
||||
@ -1,23 +0,0 @@
|
||||
lint_rtl
|
||||
This goal checks;
|
||||
- Basic connectivity issues in the design, such as floating input, width mismatch, etc.
|
||||
- Simulation issues such as incomplete sensitivity list, incorrect use of blocking/non-blocking
|
||||
assignments, potential functional errors possible simulation hang cases, and simulation race cases
|
||||
- Structural issues in the design that affect the post-implementation functionality or
|
||||
performance of the design. Examples include multiple drivers, high fan-in mux, and
|
||||
synchronous/asynchronous use of resets.
|
||||
- Synthesizable constructs in the design and code which can cause RTL vs. gate simulation mismatch.
|
||||
|
||||
Ideally this goal should be run before checking in new RTL changes.
|
||||
|
||||
design_audit (Optional)
|
||||
This goal provides design audit information. The aim of this goal is to gather statistics
|
||||
of the design. These may include information on the Top level design, Black/Gray Boxes,
|
||||
Parameters/Generics etc, and information on the design size, control signals etc.
|
||||
|
||||
clock_reset_integrity
|
||||
The aim of this goal is to check the integrity of clock and reset architecture in the design.
|
||||
Such as the following;
|
||||
* Possible race condition between clock and enable of FFs
|
||||
* Complex Issues like Gated Clock or deep ripple clock divider
|
||||
|
||||
@ -1,126 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : design_audit
|
||||
// Version: 2.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date SG Ver Comments
|
||||
// 1.0.0 18-Feb-2013 5.0 Initial version
|
||||
// 1.1.0 31-May-2013 5.1 Removed Following Rules:
|
||||
// Audit2Stats2
|
||||
// Added following Rules:
|
||||
// Audit2Stats3
|
||||
// 2.0.0 30-May-2014 5.3 Guidware 2.0 Content Consistency
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
lint/design_audit
|
||||
*
|
||||
Reports informational data related to design
|
||||
|
||||
*
|
||||
This goal helps in profiling the block, as well as gathering some useful
|
||||
statistics for the design. It may not be needed when RTL is still being actively
|
||||
coded. However, when RTL is somewhat complete, this information is useful to get
|
||||
an overall profile of the design.
|
||||
In later stages of RTL development, a sudden change in design characteristics
|
||||
(say, number of FFs) may point to unintended or non-optimal bug-fix. This
|
||||
goal should be run once per week.
|
||||
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=Audits,area,erc,clock-reset,spyglass,starc,lint,morelint
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
-sel_case_analysis_mode="direct"
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-rules Audit2Stats7a // Gives the libraries that are declared but not used in the design unit
|
||||
-overloadrules Audit2Stats7a+severity=Info
|
||||
|
||||
-rules Audit2ID // Gathers stats for design. Do not select this rule directly
|
||||
-overloadrules Audit2ID+severity=Data
|
||||
|
||||
-rules Audit2Stats // Evaluates the number of input, output and inout ports in a module
|
||||
-overloadrules Audit2Stats+severity=Data
|
||||
|
||||
-rules Audit2Stats3 // Evaluates the sum total of each of one-dimensional and multi-dimensionalbuses used in a design on rtl level
|
||||
-overloadrules Audit2Stats3+severity=Data
|
||||
|
||||
-rules Audit2Stats4 // Dumps the generic used per entity.
|
||||
-overloadrules Audit2Stats4+severity=Info
|
||||
|
||||
-rules Audit2Stats7b // Gives all the libraries declared for entity and architecture.
|
||||
-overloadrules Audit2Stats7b+severity=Info
|
||||
|
||||
-rules Audit2Stats8 // Evaluates the number of times each blackbox is instantiated.
|
||||
-overloadrules Audit2Stats8+severity=Info
|
||||
|
||||
-rules Audit4ID // Gathers stats for design. Do not select this rule directly
|
||||
-overloadrules Audit4ID+severity=Data
|
||||
|
||||
-rules DirectiveCheck-ML // Rule dumps information about ifdef, undef and include directives used in design
|
||||
-overloadrules DirectiveCheck-ML+severity=Data
|
||||
|
||||
-rules PragmaComments-ML // Pragma Comments have been detected.
|
||||
-overloadrules PragmaComments-ML+severity=Data
|
||||
|
||||
-rules STARC-1.6.6.3 // Do not directly instantiate cells in the design
|
||||
-overloadrules STARC-1.6.6.3+severity=Info
|
||||
|
||||
-rules Audit2Stats5 // Dumps the data regarding line of codes, lines of comment, per architecture.
|
||||
-overloadrules Audit2Stats5+severity=Data
|
||||
|
||||
-rules Audit2Stats6 // Dumps the data regarding line of codes, lines of comment, for entire design
|
||||
-overloadrules Audit2Stats6+severity=Data
|
||||
|
||||
-rules Audit2FileNameDump // Dumps the information regarding which module is defined in which file.
|
||||
-overloadrules Audit2FileNameDump+severity=Data
|
||||
|
||||
-rules ReportPortInfo-ML // Generate a report of all ports of top level block and black-box instances.
|
||||
-overloadrules ReportPortInfo-ML+severity=Data
|
||||
|
||||
-rules RegInputOutput-ML // Module output and input port should be registered
|
||||
-overloadrules RegInputOutput-ML+severity=Data
|
||||
-chkTopModule="yes" // Rule checkign will be done only for top module
|
||||
|
||||
-rules W438 // Tri-state used below top-level of design
|
||||
-overloadrules W438+severity=Info
|
||||
|
||||
-rules GateCount // Reports Gate count and Instance Count for the complete hierarchy of design
|
||||
-overloadrules GateCount+severity=Data
|
||||
-rptallmodulegatecount="yes" // This parameter helps user to dump gate count of all modules in vdb file.
|
||||
|
||||
-rules Audit4Dump // Dumps the information regarding number of flip-flops, latches and tristates(evaluated in rule Audit4count) on stdout.
|
||||
-overloadrules Audit4Dump+severity=Data
|
||||
|
||||
-rules AuditReportCell // Dumps the information regarding library cells
|
||||
|
||||
-rules listTristateBuses // List all tristate busses used in the design.
|
||||
|
||||
-rules Clock_info01 // Reports likely clock signals
|
||||
|
||||
-rules Reset_info01 // Reports likely asynchronous and synchronous preset and clear signals
|
||||
|
||||
-rules Setup_clock01 // Generates information needed for Clock Setup
|
||||
|
||||
-rules Audit4Count // Evaluates the number of Flip-flops, latches and tristates in a moduleThis is done on flat level netlist
|
||||
-overloadrules Audit4Count+severity=Data
|
||||
@ -1,65 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
|
||||
<head>
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />
|
||||
<meta http-equiv="Content-Style-Type" content="text/css" />
|
||||
<meta name="GENERATOR" content="Quadralay WebWorks Publisher 2003 for FrameMaker 8.0.8.2296" />
|
||||
<meta name="TEMPLATEBASE" content="Atrenta 1.0" />
|
||||
<meta name="LASTUPDATED" content="05/10/10 16:51:08" />
|
||||
<title>block_profile</title>
|
||||
<link rel="StyleSheet" href="document.css" type="text/css" />
|
||||
<link rel="StyleSheet" href="catalog.css" type="text/css" />
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/context.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/towwhdir.js"></script>
|
||||
<script type="text/javascript" language="JavaScript1.2" src="wwhdata/common/wwhpagef.js"></script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Set reference to top level help frame
|
||||
//
|
||||
var WWHFrame = WWHGetWWHFrame("");
|
||||
// -->
|
||||
</script>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2" src="scripts/expand.js"></script>
|
||||
</head>
|
||||
|
||||
<body onLoad="WWHUpdate();" onUnload="WWHUnload();" onKeyDown="WWHHandleKeyDown((document.all||document.getElementById||document.layers)?event:null);" onKeyPress="WWHHandleKeyPress((document.all||document.getElementById||document.layers)?event:null);" onKeyUp="WWHHandleKeyUp((document.all||document.getElementById||document.layers)?event:null);">
|
||||
|
||||
<hr align="left" />
|
||||
|
||||
<blockquote>
|
||||
<a name="wp1131431"> </a><h2 class="pHeading1">
|
||||
block_profile
|
||||
</h2>
|
||||
<a name="wp1131463"> </a><p class="pBody">
|
||||
This goal helps in profiling the block, as well as gathering some useful statistics for the design. It may not be needed when RTL is still being actively coded. However, when RTL is somewhat complete, this information is useful to get an overall profile of the design. In later stages of RTL development, a sudden change in design characteristics (say, number of FFs) may point to unintended or non-optimal bug-fix.
|
||||
</p>
|
||||
|
||||
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
// Clear related topics
|
||||
//
|
||||
WWHClearRelatedTopics();
|
||||
|
||||
// -->
|
||||
</script>
|
||||
</blockquote>
|
||||
|
||||
<hr />
|
||||
|
||||
<table id="SummaryNotReq1" align="right" border="0" cellspacing="0" cellpadding="0">
|
||||
|
||||
</table>
|
||||
|
||||
<script type="text/javascript" language="JavaScript1.2">
|
||||
<!--
|
||||
document.write(WWHRelatedTopicsDivTag() + WWHPopupDivTag() + WWHALinksDivTag());
|
||||
// -->
|
||||
</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@ -1,46 +0,0 @@
|
||||
// ----------------------------------------------------------------------------
|
||||
// SpyGlass GuideWare2.0 Goal File
|
||||
//
|
||||
// Goal Name : lint_abstract
|
||||
// Version: 2.0.0
|
||||
//
|
||||
// Revision History:
|
||||
// Ver Date Comments
|
||||
// 1.0.0 18-Feb-2013 Initial version
|
||||
// 2.0.0 30-May-2014 5.3 Guidware 2.0 Content Consistency
|
||||
//
|
||||
// Copyright Atrenta Inc, 2015. All rights reserved.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
=template++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
lint_abstract
|
||||
*
|
||||
Generates relevant base policy(lint) constraints for block abstraction
|
||||
*
|
||||
This goal helps in generating an abstracted model of a block. The abstracted
|
||||
model will be used during SoC-level validation and verification.
|
||||
|
||||
=cut+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-policy=lint
|
||||
|
||||
//------------------------------------------------
|
||||
// General Setup commands
|
||||
//------------------------------------------------
|
||||
|
||||
//------------------------------------------------
|
||||
// Policy Specific Parameter Setting
|
||||
//------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------
|
||||
// Rule Registration
|
||||
//------------------------------------------------
|
||||
|
||||
-block_abstract
|
||||
-rules LINT_abstract01 // Generates relevant base policy constraints for block abstraction
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue