5 Commits (db09feff98ef9e5edecc4a1b92c57badd5a08372)

 

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Author	SHA1	Message	Date
pl5g92irw	db09feff98	Merge pull request '初始文件同步' (#1) from ready into master	3 years ago
pl5g92irw	48bebc411a	FPGA神经网络所重复调动的函数模块，Verilog语言	3 years ago
pl5g92irw	267521f871	以Verilog语言实现FPGA神经网络	3 years ago
pl5g92irw	3240e076ea	Python描述的神经网络模型	3 years ago
pl5g92irw	92fa790709	Initial commit	3 years ago