formatted

code/adder.py

@@ -1,2 +1,2 @@
-def adder(a,b):                         #返回加法运算结果y
+def adder(a, b):  # 返回加法运算结果y
-    return a+b
+    return a + b

code/alu.py

@@ -38,11 +38,11 @@ def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，
             alu_result = 0
     elif alu_ctrl == '01001':
         if a < 0:
-            ua = a + 2**32
+            ua = a + 2 ** 32
         else:
             ua = a
         if b < 0:
-            ub = b + 2**32
+            ub = b + 2 ** 32
         else:
             ub = b
         if ua < ub:
@@ -51,11 +51,11 @@ def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，
             alu_result = 0
     elif alu_ctrl == '01010':
         if a < 0:
-            ua = a + 2**32
+            ua = a + 2 ** 32
         else:
             ua = a
         if b < 0:
-            ub = b + 2**32
+            ub = b + 2 ** 32
         else:
             ub = b
         if ua >= ub:
@@ -70,11 +70,11 @@ def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，
         alu_result = a << b
     elif alu_ctrl == '01110':
         if a < 0:
-            ua = a + 2**32
+            ua = a + 2 ** 32
         else:
             ua = a
         if b < 0:
-            ub = b + 2**32
+            ub = b + 2 ** 32
         else:
             ub = b
         if ua <= ub:
@@ -83,7 +83,7 @@ def alu(a, b, alu_ctrl):  # a,b为两个运算数，alu_ctrl为控制信号，
             alu_result = 0
     elif alu_ctrl == '01111':
         if a < 0:
-            ua = a + 2**32
+            ua = a + 2 ** 32
         else:
             ua = a
         alu_result = a >> b

code/binandint.py

@@ -1,7 +1,7 @@
 def BintoInt(x):
     i = int(x, base=2)
     if x[0] == '1':
-        i = i - 2**len(x)
+        i = i - 2 ** len(x)
     return i
 
 
@@ -15,9 +15,10 @@ def UInttoBin(x, n):
 
 def InttoBin(x, n):
     if x < 0:
-        x += 2**n
+        x += 2 ** n
     return UInttoBin(x, n)
 
+
 def unsigned_ext(x, n):
     return '0' * (n - len(x)) + x
 

code/branch_unit.py

@@ -1,10 +1,14 @@
-def branch_unit(cur_pc, imm, jalr_sel, branch_taken,
+from typing import Tuple
-                alu_result):  # 输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型)
+
+
+def branch_unit(
+        cur_pc: int, imm: int, jalr_sel: int, branch_taken: int, alu_result: int
+) -> Tuple[int, int, int, int]:  # 输入值为当前pc（int），立即数，jalr信号，是否跳转信号，alu运算结果(全是int型)
     pc_plus_4 = cur_pc + 4  # 输出为pc_plus_imm,pc_plus_4,branch_target,pc_sel(忘了这是啥了，需要回头再看)
     pc_plus_imm = cur_pc + imm
     pc_sel = jalr_sel | (branch_taken & (alu_result % 2))
     if jalr_sel == 1:
-        branch_target = alu_result & (2**32 - 2)
+        branch_target = alu_result & (2 ** 32 - 2)
     else:
         branch_target = cur_pc + imm * 2
     return pc_plus_imm, pc_plus_4, branch_target, pc_sel

code/data_mem.py

@@ -11,9 +11,9 @@ class data_mem:
             ):  # 写使能，读使能，(使能为int的0或1)地址，输入数据，func3              #输出为data_out
         if write_en:
             if funct3 == '000':  # sb
-                self.memory[address] = InttoBin(data_in % 2**8, 8)
+                self.memory[address] = InttoBin(data_in % 2 ** 8, 8)
             elif funct3 == '001':  # sh
-                temp = InttoBin(data_in % 2**16, 16)
+                temp = InttoBin(data_in % 2 ** 16, 16)
                 self.memory[address + 1] = temp[0:8]
                 self.memory[address] = temp[8:16]
             elif funct3 == '010':  # sw

code/insn_mem.py

@@ -1,10 +1,10 @@
 class insn_mem:
-    memory = [8*'0']*4*1024*16
+    memory = [8 * '0'] * 4 * 1024 * 16
 
     def __init__(self) -> None:
         pass
 
     def fetch(self, address):
-        insn = self.memory[address+3]+self.memory[address+2] + \
+        insn = self.memory[address + 3] + self.memory[address + 2] + \
-            self.memory[address+1]+self.memory[address]
+               self.memory[address + 1] + self.memory[address]
         return insn

code/mux.py

@@ -1,5 +1,5 @@
-def mux(d0,d1,s):               #返回选择结果
+def mux(d0, d1, s):  # 返回选择结果
-    if s=='0':
+    if s == '0':
         return d0
     else:
-        return d1
+        return d1

code/mux4.py

@@ -1,9 +1,9 @@
-def mux4(d00,d01,d10,d11,s):            #返回选择结果
+def mux4(d00, d01, d10, d11, s):  # 返回选择结果
-    if s=='00':
+    if s == '00':
         return d00
-    elif s=='01':
+    elif s == '01':
         return d01
-    elif s=='10':
+    elif s == '10':
         return d10
     else:
-        return d11
+        return d11

code/proc_controller.py

@@ -1,25 +1,25 @@
 def proc_controller(opcode):
-    if opcode=='0110011':   #(add,and,or,sll,slt,sltu,sra,srl,sub,xor)
+    if opcode == '0110011':  # (add,and,or,sll,slt,sltu,sra,srl,sub,xor)
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','1','0','0','10','0','0','00'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '1', '0', '0', '10', '0', '0', '00'
-    elif opcode=='0110111': #(lui)20位立即数
+    elif opcode == '0110111':  # (lui)20位立即数
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','1','0','0','00','0','0','10'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '1', '0', '0', '00', '0', '0', '10'
-    elif opcode=='1101111': #(jal)
+    elif opcode == '1101111':  # (jal)
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','11','1','0','01'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '11', '1', '0', '01'
-    elif opcode=='0010011': #(addi,andi,ori,slli,slti,sltiu,srai,srli,xori)
+    elif opcode == '0010011':  # (addi,andi,ori,slli,slti,sltiu,srai,srli,xori)
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','10','0','0','00'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '10', '0', '0', '00'
-    elif opcode=='0000011': #(lb,lbu,lh,lhu,lw)
+    elif opcode == '0000011':  # (lb,lbu,lh,lhu,lw)
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','1','1','1','0','00','0','0','00'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '1', '1', '1', '0', '00', '0', '0', '00'
-    elif opcode=='1100111': #(jalr)
+    elif opcode == '1100111':  # (jalr)
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','10','1','1','01'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '10', '1', '1', '01'
-    elif opcode=='0100011': #(sb, sh, sw)
+    elif opcode == '0100011':  # (sb, sh, sw)
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','0','0','1','00','0','0','00'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '0', '0', '1', '00', '0', '0', '00'
-    elif opcode=='1100011': #(beq,bge,bgeu,blt,bne,bltu)
+    elif opcode == '1100011':  # (beq,bge,bgeu,blt,bne,bltu)
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','0','0','0','01','1','0','00'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '0', '0', '0', '01', '1', '0', '00'
-    elif opcode=='1101111': #(jal)
+    elif opcode == '1101111':  # (jal)
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','11','1','0','01'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '11', '1', '0', '01'
-#################################
+    #################################
-    elif opcode=='0010111': #(auipc)20位立即数
+    elif opcode == '0010111':  # (auipc)20位立即数
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='1','0','1','0','0','00','1','0','10'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '1', '0', '1', '0', '0', '00', '1', '0', '10 '
     else:
-        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel='0','0','0','0','0','00','0','0','00'
+        ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel = '0', '0', '0', '0', '0', '00', '0', '0', '00'
-    return ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel
+    return ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, ALUOp, Branch, JalrSel, RWSel

code/reg_file.py

@@ -1,5 +1,5 @@
 class reg_file:
-    regs = [0]*32
+    regs = [0] * 32
 
     def __init__(self) -> None:
         pass

code/top(wating_to_filling).py

@@ -1,4 +1,4 @@
 from datapath import *
 
 if __name__ == '__main__':
-    dataPath()
+    dataPath()