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248 Commits (ca6c9fa5407edbc1bb9d91a4697dbeff954e91d2)
 

Author SHA1 Message Date
lzkk ca6c9fa540 docs: 记录 MAX_SPILL_ROUNDS 修复——mm1 指令数削减 99.4%
5 days ago
lzkk d238777f17 fix(regalloc): 根除 spill 代码指数级膨胀——MAX_SPILL_ROUNDS 统一为 3
5 days ago
lzkk 535ab08d32 feat(backend): AsmPrinter 帧基址缓存，避免连续栈访问重复计算地址
5 days ago
lzkk 3ab88232f7 fix(hooks): Stop hook 改为智能检测——仅在 src/ 有未提交改动时提醒
5 days ago
lzkk 6f14ee1a7a fix(infra): 编译器资源限制包装器 + 测试脚本超时防护，防止 OOM 闪退
5 days ago
lzkk 5300e2c1ec fix(hooks): 修复会话崩溃 + 优化开发规范配置
5 days ago
lzkk da5d618297 fix(hooks): memory-guard 输出合法 JSON，修复会话崩溃
5 days ago
lzkk 2d3a5ff998 perf(backend): Peephole 新增全局变量 store-load 转发和 load CSE
5 days ago
lzkk b2b7210f11 perf(backend): 除法/取模统一使用 sdiv，删除2的幂次移位序列
5 days ago
lzkk befdca6451 perf(backend): 叶函数跳过帧设置，节省 x29/x30 保存/恢复
5 days ago
lzkk 854168fb4e perf(backend): 消除连续全局变量访问的冗余 ADRP
5 days ago
lzkk acdac5391d fix(backend): EmitLargeImmediate 跳过前导零，避免冗余 movz #0
5 days ago
lzkk bb58aac749 fix(mem2reg): 添加大参数函数安全门禁，修复 87_many_params
5 days ago
lzkk fccd935a24 feat(backend): 新增 AddImm/SubImm 操作码，消除冗余 MovImm
5 days ago
lzkk bd7dcedb2a feat(backend): ICmp 降级常量折叠到 CmpImm，消除冗余 MovImm
6 days ago
黄熙哲 6b9cf3a448 fix(backend): add x16/x17 to GP allocatable set to fix segfaults
6 days ago
黄熙哲 5902060dae fix(backend): lower coalesce skip threshold to fix segfaults
6 days ago
黄熙哲 34cb79449f fix(backend): skip coalescing for large functions to prevent segfault\n\nFor functions with >150 vregs, discard move_preferences after\ncollection to skip active coalescing. Large functions like\nconv2d, 65_color, 68_brainfk have complex interference graphs\nthat cause coalescing to generate incorrect spill code.\n\nFixes segfaults in: conv2d-1/2/3, 65_color, 68_brainfk, 37_dct.\n\nKnown limitations: 30_many_dimensions and 39_fp_params still\nsegfault (pre-existing original compiler bugs in lowering/RA).\nMinor instruction count changes: h-8 +2.5%, matmul +7% etc.
7 days ago
黄熙哲 a84ffd210b chore: simplify baseline to single-column historical minimum\n\nRemove source baseline concept. Each test now tracks only its\nbest-ever instruction count. count_asm.sh updated to directly\nupdate baseline when a new lower value is found.
7 days ago
黄熙哲 b7e78ebd56 fix(backend): AsmPrinter large frame + RegAlloc spill limit\n\nApply only proven-safe fixes on clean baseline:\n- AsmPrinter: movz/movk for large stack offsets (>12KB)\n 30_many_dimensions: 7M -> 1455 lines (99.9% reduction)\n- RegAlloc: limit spill rounds to 3 for large functions (>120 vregs)\n 39_fp_params: >120s -> <1s compilation\n\nZero instruction count regression confirmed.\n57/60 performance tests at historical best baseline.
7 days ago
黄熙哲 2e368f86cf chore: update instruction count baseline after Mem2Reg threshold tuning\n\nKey improvements from PHI threshold relaxation:\n- many_mat_cal: 523->432 (-91 lines, 17.4%)\n- h-8: 504->407 (-97 lines, 19.2%)\n- matmul: 450->366 (-84 lines, 18.7%)\n\nCrypto and other complex functions unaffected (correctly skipped).
1 week ago
黄熙哲 cc9f4f9a76 feat(mem2reg): tune PHI threshold to allow Mem2Reg on moderate functions\n\nChange phi_threshold from max(50, block_count) to max(100, block_count*2).\nThe old threshold was too conservative for functions with many allocas\nlike many_mat_cal (~15 allocas, 60 blocks), causing premature skip.\nThe new threshold allows these while still blocking crypto-like functions\nwhere excessive PHI nodes hurt code quality.\n\nmany_mat_cal: -91 lines, matmul: -84 lines, h-8: -97 lines
1 week ago
黄熙哲 d5d8924050 chore: update instruction count baseline after loop optimizations merge\n\nAdditional reductions from loop IR passes:\n- conv2d: 657->629 (-28), fft: 619->605 (-14)\n- huffman: 849->829 (-20), sl: 280->264 (-16)\n- knapsack: 175->167 (-8), transpose: 211->207 (-4)\n- 01_mm: 313->310 (-3), h-10: 335->329 (-6)\n\nRestore CLAUDE.md deleted during merge.
1 week ago
黄熙哲 06bada3ff5 Merge remote master into local master
1 week ago
黄熙哲 39b7e2ed19 feat(backend): loop-depth weighted spill cost model\n\nAdds DFS-based back-edge detection to compute basic block loop\nnesting depth. Each vreg inherits the max loop depth of its\ndefining blocks. Spill cost multiplies interval+ref by 10^depth,\nmaking loop-carried variables much more expensive to spill.
1 week ago
黄熙哲 993e81363a fix(backend): recompute degree unconditionally after MergeInto\n\nAfter a merge, u inherits v's neighbors, so degree[u] must always\nbe recomputed. Previously, when degree[u] < K before merge, the\nstale low degree was kept, which could push a high-degree merged\nnode into simplify_worklist with wrong metadata.\n\nAlso remove redundant if(!remaining.empty()) guard in spill path\nand clean up extra brace from removed GiveUpPhase.
1 week ago
黄熙哲 bef03ec220 chore: update instruction count baseline after Module D rewrite\n\n54/60 performance tests reduced. Key improvements:\n- conv2d: -95 lines (12.6%)\n- huffman: -44 lines (4.9%)\n- fft: -39 lines (5.9%)\n- crc: -38 lines (11.6%)\n- 03_sort: -28 lines (4.2%)\n- 01_mm: -22 lines (6.6%)\n\nAlso fix count_asm.sh sed to match any current value.
1 week ago
黄熙哲 570253f1f2 feat(backend): relax Briggs threshold to 2*K and fix move_adj self-loop\n\nUsing >= 2*K instead of >= K for high-degree neighbor count allows\nmore node pairs to be safely merged. Fixed a bug in MergeInto where\nmove_adj[u] could contain u (self-loop) when v's move set included u,\ncausing iterator invalidation during move_adj cleanup.
1 week ago
黄熙哲 3691da34ee feat(backend): rewrite main loop with held_nodes release and ReactivatePairs
1 week ago
黄熙哲 0881889ec1 feat(backend): add ReactivatePairs and stale_pairs for coalescing
1 week ago
黄熙哲 07048a123b feat(backend): separate move-related low-degree nodes into held_nodes
1 week ago
黄熙哲 99fe17fc3f feat(backend): propagate coalesced node colors in AssignColors\n\nAfter active coalescing, merged_set nodes inherit their representative's\ncolor, ensuring move-related vregs share the same physical register.
1 week ago
黄熙哲 081580ac0a feat(backend): integrate active coalescing into ColorGraph main loop\n\nReplaces inner simplify while-loop with if-else chain:\nSimplify -> MergePhase -> GiveUpPhase -> Spill.\nLambdas moved outside while loop for clarity.
1 week ago
黄熙哲 0e4f9f1910 feat(backend): add MergePhase and GiveUpPhase for active coalescing\n\nMergePhase uses the Briggs conservative test to safely merge move-related\nnode pairs before coloring. GiveUpPhase abandons moves for low-degree\nnodes when merging is no longer beneficial.
1 week ago
黄熙哲 ca6c2a18c9 feat(backend): add coalesce data structures and helpers to ColorGraph\n\nIntroduces MovePair, move_adj, FindRep, GetRep, HasMovePair as\ninfrastructure for the upcoming Coalesce and Freeze phases.\nModifies simplify loop to skip already-merged nodes via GetRep.
1 week ago
黄熙哲 560f565a51 chore: update instruction count baseline after Module B stp/ldp\n\nAlso modify count_asm.sh to auto-update baseline when instruction\ncounts decrease below the recorded values.
1 week ago
黄熙哲 af71513361 feat(backend): use stp/ldp for callee-saved registers in prologue/epilogue\n\nGroups callee-saved X and S registers and emits paired stp/ldp\ninstructions, reducing save/restore overhead by ~50%. Odd remainders\nstill use str/ldr. Adds fallback else branch for future register types.
1 week ago
安峻邑 cb33c344ac 启动循环优化
1 week ago
安峻邑 b93e81ce74 循环优化
1 week ago
安峻邑 4bc21faf61 循环优化
1 week ago
安峻邑 d07bf9f0d2 循环优化
1 week ago
安峻邑 81b5c2a2b0 循环优化
1 week ago
安峻邑 860e5edadf 实现循环优化：LICM、强度削弱、循环展开、循环分裂
1 week ago
黄熙哲 e26fd3f520 fix(peephole): remove dead conditional branch inversion code\n\nThe CondBr+Branch inversion pattern was unreachable because the\nsimple Br fallthrough check runs first and removes the Br. Removed\nthe dead code and the unused NegateCondCode helper.
1 week ago
黄熙哲 7490fd3a49 feat(peephole): add branch fallthrough and conditional branch inversion\n\nEliminates unconditional Br when target is the next block in layout.\nInverts CondBr condition when the following Br targets the fallthrough\nblock, eliminating the extra jump.
1 week ago
黄熙哲 1701b2cf51 feat(peephole): merge adjacent zero-value stack stores\n\nWhen str WZR, fi#N and str WZR, fi#N+1 appear consecutively,\nreplaces them with a single str XZR, fi#N (64-bit zero store).
1 week ago
黄熙哲 e44ba819ec feat(peephole): add store-load forwarding pattern\n\nWhen StoreStack regA, fi#N is immediately followed by LoadStack regB, fi#N\nwith regA != regB, replaces the load with MovReg regB, regA, eliminating\nthe redundant memory access.
1 week ago
黄熙哲 083616e50d fix(backend): add redundant MovReg elimination on no-spill early-return path\n\nThe MovReg cleanup was only running after the final RewriteWithAllocation\nat the end of the spill loop, missing the early-return path when\nallocation succeeded without spilling. This left behind no-op moves\nlike 'mov x0, x0' that coalescing created.
1 week ago
黄熙哲 6f829c30f9 feat(backend): eliminate redundant MovReg after register allocation\n\nScans all blocks after RewriteWithAllocation and removes MovReg\ninstructions where source and destination are the same physical\nregister. This cleans up cases where move coalescing successfully\nassigned the same register to both sides.
1 week ago
黄熙哲 4bdca3f722 feat(backend): move coalescing via color preference and phi cycle breaking\n\nCollects move_preferences from MovReg instructions and uses them\nduring color selection to prefer the same physical register for\nmove-related virtual registers. Detects and breaks cycles in move\npreference chains to ensure correctness.
1 week ago